Hyun-Kyu Yu

According to our database, Hyun-Kyu Yu authored at least 17 papers between 1999 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

A 230ns settling time type-I PLL with 0.96mW TDC power and simple TV calculation algorithm.

Ja-Yol Lee, Mi-Jeong Park, Hyun-Kyu Yu, Cheon-Soo Kim

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2013

1-5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector.

Sangjin Byun, Chung Hwan Son, Jongil Hwang, Byung-Hun Min, Mun-Yang Park, Hyun-Kyu Yu

IET Circuits Devices Syst., 2013

2012

A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation.

Ja-Yol Lee, Mi-Jeong Park, Byung-Hun Min, Seongdo Kim, Mun-Yang Park, Hyun-Kyu Yu

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

2011

A digital-intensive receiver front-end using VCO-based ADC with an embedded 2nd-Order anti-aliasing Sinc filter in 90nm CMOS.

Jaewook Kim, Wonsik Yu, Hyun-Kyu Yu, SeongHwan Cho

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A low power discrete-time receiver for triple-band FM/T-DMB/DAB system-on-chip.

Hoai-Nam Nguyen, Seung-Hwan Jung, Byung-Hun Min, Young-Jae Lee, Sang-Gug Lee, Yun Seong Eo, Hyun-Kyu Yu

Proceedings of the 37th European Solid-State Circuits Conference, 2011

2008

A 20 Gb/s 1: 4 DEMUX Without Inductors and Low-Power Divide-by-2 Circuit in 0.13 µm CMOS Technology.

Byung-Guk Kim, Lee-Sup Kim, Sangjin Byun, Hyun-Kyu Yu

IEEE J. Solid State Circuits, 2008

2006

A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector.

Sangjin Byun, Jyung Chan Lee, Jae Hoon Shim, Kwangjoon Kim, Hyun-Kyu Yu

IEEE J. Solid State Circuits, 2006

A 20gb/s 1: 4 DEMUX without inductors in 0.13µm CMOS.

Byung-Guk Kim, Lee-Sup Kim, Sangjin Byun, Hyun-Kyu Yu

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 10Gb/s CMOS CDR and DEMUX IC with a Quarter-Rate Linear Phase Detector.

Sangjin Byun, Jyung Chan Lee, Jae Hoon Shim, Kwangjoon Kim, Hyun-Kyu Yu

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A transformer-based low phase noise and widely tuned CMOS quadrature VCO.

Young-Jae Lee, Hyun-Kyu Yu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

Automatic tuning circuit for Gm-C filters.

Young-Ho Kim, Hyun-Kyu Yu

Proceedings of the 12th IEEE International Conference on Electronics, 2005

2004

An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter.

Byung-Do Yang, Jang-Hong Choi, Seon-Ho Han, Lee-Sup Kim, Hyun-Kyu Yu

IEEE J. Solid State Circuits, 2004

Subharmonically pumped CMOS frequency conversion (up and down) circuits for 2-GHz WCDMA direct-conversion transceiver.

Kwang-Jin Koh, Mun-Yang Park, Cheon-Soo Kim, Hyun-Kyu Yu

IEEE J. Solid State Circuits, 2004

A 1.8V triode-type transconductor and its application to a 10MHz 3^rd-order Chebyshev low pass filter.

Young-Ho Kim, Jung-Woo Park, Mun-Yang Park, Hyun-Kyu Yu

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2002

A high speed direct digital frequency synthesizer using a low power pipelined parallel accumulator.

Byung-Do Yang, Lee-Sup Kim, Hyun-Kyu Yu

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A gain boosting method at RF frequency using active feedback and its application to RF variable gain amplifier (VGA).

Kwang-Jin Koh, Yong-Sik Youn, Hyun-Kyu Yu

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

1999

A process and environment tolerant 3V, 2 GHz VCO with 0.8 μm CMOS technology.

Keewook Jung, Changsik Yoo, Hyun-Kyu Yu, Wonchui Song, Wonchan Kim

IEEE Trans. Consumer Electron., 1999