Mutsuo Daito

According to our database, Mutsuo Daito authored at least 5 papers between 2006 and 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2011

Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing.

Mutsuo Daito, Yoshiro Nakata, Satoshi Sasaki, Hiroyuki Gomyo, Hideki Kusamitsu, Yoshio Komoto, Kunihiko Iizuka, Katsuyuki Ikeuchi, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai

IEEE J. Solid State Circuits, 2011

1 Gb/s, 50 µm × 50 µm Pads on Board Wireless Connector Based on Track-and-Charge Scheme Allowing Contacted Signaling.

Katsuyuki Ikeuchi, Hideki Kusamitsu, Mutsuo Daito, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai

IEICE Trans. Electron., 2011

2010

A high-speed, low-power capacitive-coupling transceiver for wireless wafer-level testing systems.

Gil-Su Kim, Katsuyuki Ikeuchi, Mutsuo Daito, Makoto Takamiya, Takayasu Sakurai

Proceedings of the IEEE International Conference on 3D System Integration, 2010

2006

A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s.

Kunihiko Iizuka, Hirofumi Matsui, Masaya Ueda, Mutsuo Daito

IEEE J. Solid State Circuits, 2006

A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration.

Mutsuo Daito, Hirofumi Matsui, Masaya Ueda, Kunihiko Iizuka

IEEE J. Solid State Circuits, 2006