Kunihiko Iizuka

According to our database1, Kunihiko Iizuka authored at least 24 papers between 1996 and 2016.

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Bibliography

2016
CMOS Biosensor IC Focusing on Dielectric Relaxations of Biological Water With 120 and 60 GHz Oscillator Arrays.
IEEE J. Solid State Circuits, 2016

An Analog Front-End for a Multifunction Sensor Employing a Weak-Inversion Biasing Technique With 26 nVrms, 25 aCrms, and 19 fArms Input-Referred Noise.
IEEE J. Solid State Circuits, 2016

28.3 CMOS biosensor IC focusing on dielectric relaxations of biological water with 120GHz and 60GHz oscillator arrays.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
97-mW 8-Phase CMOS VCO and Dividers for a 134-GHz PLL Synthesizer.
IEICE Trans. Electron., 2015

A 24-bit multi-functional sensor analog front end employing low noise biasing technique with 8.2nV/√Hz input referred noise.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
8-GHz Locking Range and 0.4-pJ Low-Energy Differential Dual-Modulus 10/11 Prescaler.
IEICE Trans. Electron., 2014

9dB NF and +11dBm OIP3 CMOS Single Conversion Front-End for a Satellite Low-Noise Block Down-Converter.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

2011
Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing.
IEEE J. Solid State Circuits, 2011

2010
Foreword.
IEICE Trans. Electron., 2010

2009
A 100 MS/s 4 MHz Bandwidth 70 dB SNR ΔΣ ADC in 90 nm CMOS.
IEEE J. Solid State Circuits, 2009

2008
RF Variable-Gain Amplifiers and AGC Loops for Digital TV Receivers.
IEICE Trans. Electron., 2008

2007
A Digitally Controlled Variable-Gain Low-Noise Amplifier With Strong Immunity to Interferers.
IEEE J. Solid State Circuits, 2007

A 184 mW Fully Integrated DVB-H Tuner With a Linearized Variable Gain LNA and Quadrature Mixers Using Cross-Coupled Transconductor.
IEEE J. Solid State Circuits, 2007

A Digital TV Receiver RF and BB Chipset with Adaptive Bias-Current Control for Mobile Applications.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s.
IEEE J. Solid State Circuits, 2006

A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration.
IEEE J. Solid State Circuits, 2006

Fast Automatic Tuning of Channel Selection Filters Based on Phase Delay Calibration.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
A high OIP3 quadrature mixer using cross-coupled transconductor.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2002
Embedded anti-aliasing in switched-capacitor ladder filters with variable gain and offset compensation.
IEEE J. Solid State Circuits, 2002

2001
CDMA functional blocks using recycling integrator correlators-matched filters and delay-locked loops.
IEEE J. Solid State Circuits, 2001

Embedded anti-aliasing in switched-capacitor ladder filters.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000
A 2-V 3.7-mW delay locked-loop using recycling integrator correlators for a 5-Mcps DS-CDMA demodulator.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999
A parallel analog intelligent vision sensor with a variable receptive field.
Syst. Comput. Jpn., 1999

1996
Dynamically Adaptable CMOS Winner-Take-All Neural Network.
Proceedings of the Advances in Neural Information Processing Systems 9, 1996


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