Myeonggu Kang
Orcid: 0000-0003-3557-8526
According to our database1,
Myeonggu Kang
authored at least 15 papers
between 2017 and 2023.
Collaborative distances:
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Bibliography
2023
IEEE Trans. Computers, November, 2023
Fault-Free: A Framework for Analysis and Mitigation of Stuck-at-Fault on Realistic ReRAM-Based DNN Accelerators.
IEEE Trans. Computers, July, 2023
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
2022
A Framework for Accelerating Transformer-Based Language Model on ReRAM-Based Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
S-FLASH: A NAND Flash-Based Deep Neural Network Accelerator Exploiting Bit-Level Sparsity.
IEEE Trans. Computers, 2022
Re<sup>2</sup>fresh: A Framework for Mitigating Read Disturbance in ReRAM-Based DNN Accelerators.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
2021
A Framework for Area-efficient Multi-task BERT Execution on ReRAM-based Accelerators.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Optimizing ADC Utilization through Value-Aware Bypass in ReRAM-based DNN Accelerator.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Fault-free: A Fault-resilient Deep Neural Network Accelerator based on Realistic ReRAM Devices.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
An Energy-Efficient Deep Convolutional Neural Network Training Accelerator for In Situ Personalization on Smart Devices.
IEEE J. Solid State Circuits, 2020
A Thermal-aware Optimization Framework for ReRAM-based Deep Neural Network Acceleration.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
2019
An Energy-efficient Processing-in-memory Architecture for Long Short Term Memory in Spin Orbit Torque MRAM.
Proceedings of the International Conference on Computer-Aided Design, 2019
A 47.4µJ/epoch Trainable Deep Convolutional Neural Network Accelerator for In-Situ Personalization on Smart Devices.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
TrainWare: A Memory Optimized Weight Update Architecture for On-Device Convolutional Neural Network Training.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
2017
Enhanced Long Edge First Routing Algorithm and Evaluation in Large-Scale Networks-on-Chip.
Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017