Hyein Shin
Orcid: 0000-0003-0382-4032
According to our database1,
Hyein Shin
authored at least 12 papers
between 2019 and 2024.
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Bibliography
2024
2.4 ATOMUS: A 5nm 32TFLOPS/128TOPS ML System-on-Chip for Latency Critical Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
IEEE Trans. Computers, November, 2023
Fault-Free: A Framework for Analysis and Mitigation of Stuck-at-Fault on Realistic ReRAM-Based DNN Accelerators.
IEEE Trans. Computers, July, 2023
2022
A Framework for Accelerating Transformer-Based Language Model on ReRAM-Based Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
S-FLASH: A NAND Flash-Based Deep Neural Network Accelerator Exploiting Bit-Level Sparsity.
IEEE Trans. Computers, 2022
Re<sup>2</sup>fresh: A Framework for Mitigating Read Disturbance in ReRAM-Based DNN Accelerators.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
2021
A Framework for Area-efficient Multi-task BERT Execution on ReRAM-based Accelerators.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Optimizing ADC Utilization through Value-Aware Bypass in ReRAM-based DNN Accelerator.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Fault-free: A Fault-resilient Deep Neural Network Accelerator based on Realistic ReRAM Devices.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
A Thermal-aware Optimization Framework for ReRAM-based Deep Neural Network Acceleration.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
2019
A PVT-robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural Networks.
Proceedings of the International Conference on Computer-Aided Design, 2019
An Energy-efficient Processing-in-memory Architecture for Long Short Term Memory in Spin Orbit Torque MRAM.
Proceedings of the International Conference on Computer-Aided Design, 2019