Nachiketa Das

According to our database, Nachiketa Das authored at least 7 papers between 2008 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Correction to: VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach.

Subhajit Das, Sudip Ghosh, Nachiketa Das, Santi P. Maity, Hafizur Rahaman, Reshmi Maity, Niladri Maity

Circuits Syst. Signal Process., 2018

2015

An adaptive feedback based reversible watermarking algorithm using difference expansion.

Sudip Ghosh, Nachiketa Das, Subhajit Das, Santi Prasad Maity, Hafizur Rahaman

Proceedings of the 2nd IEEE International Conference on Recent Trends in Information Systems, 2015

2014

Digital Design and Pipelined Architecture for Reversible Watermarking Based on Difference Expansion Using FPGA.

Sudip Ghosh, Nachiketa Das, Subhajit Das, Santi P. Maity, Hafizur Rahaman

Proceedings of the 2014 International Conference on Information Technology, 2014

2013

Built-in-self-test technique for diagnosis of delay faults in cluster-based field programmable gate arrays.

Nachiketa Das, Pranab Roy, Hafizur Rahaman

IET Comput. Digit. Tech., 2013

Bridging fault detection in cluster based FPGA by using Muller C element.

Nachiketa Das, Pranab Roy, Hafizur Rahaman

Comput. Electr. Eng., 2013

2011

Runtime Congestion and Crosstalk Aware Router for FPGA Using Jbits3.0 for Partial Reconfigurable Application.

Nachiketa Das, Pranab Roy, Hafizur Rahaman

Proceedings of the International Symposium on Electronic System Design, 2011

2008

On Line Testing of Single Feedback Bridging Fault in Cluster Based FPGA by Using Asynchronous Element.

Nachiketa Das, Pranab Roy, Hafizur Rahaman

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008