Nagi Naganathan

According to our database, Nagi Naganathan authored at least 8 papers between 2006 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Logic locking emulator on FPGA: A conceptual view.

Manjith Baby Sarojam Chellam, Ramasubramanian Natarajan, Nagi Naganathan

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2021

Design Space Exploration for Reducing Cost of Hardware Trojan Detection and Isolation during Architectural Synthesis.

Shathanaa Rajmohan, N. Ramasubramanian, Nagi Naganathan

J. Circuits Syst. Comput., 2021

2020

Hybrid Evolutionary Design Space Exploration Algorithm With Defence Against Third Party IP Vulnerabilities.

Shathanaa Rajmohan, N. Ramasubramanian, Nagi Naganathan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Configurable Logic Blocks and Memory Blocks for Beyond-CMOS FPGA-Based Embedded Systems.

Marshal Raj, Gopalakrishnan Lakshminarayanan, Seok-Bum Ko, Nagi Naganathan, N. Ramasubramanian

IEEE Embed. Syst. Lett., 2020

2019

Resource Efficient Metering Scheme for Protecting SoC FPGA Device and IPs in IoT Applications.

Kokila Jagadeesh, N. Ramasubramanian, Nagi Naganathan

IEEE Trans. Very Large Scale Integr. Syst., 2019

2013

Message from program chairs.

Kaijian Shi, Nagi Naganathan

Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

2008

Standards in EDA: An Introduction.

Nagi Naganathan

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2006

Low-Power Design Strategies for Mobile Computing.

A. V. S. S. Prasad, Jacob Mathews, Nagi Naganathan

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006