Kaijian Shi

According to our database1, Kaijian Shi authored at least 15 papers between 2003 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2014
Message from conference general chair.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

2013
Message from program chairs.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

Sleep transistor design in 28nm CMOS technology.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

2012
Automation of Switch Insertion and Power Network Generation in 28 nm Power-Switched Designs.
J. Low Power Electron., 2012

2011
Well tapping methodologies in power-gating design.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

2010
Low-power SOC implementation: What you need to know.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

2008
Simultaneous Sleep Transistor Insertion and Power Network Synthesis for Industrial Power Gating Designs.
J. Comput., 2008

Area and power-delay efficient state retention pulse-triggered flip-flops with scan and reset capabilities.
Proceedings of the 26th International Conference on Computer Design, 2008

2007
A wakeup rush current and charge-up time analysis method for programmable power-gating designs.
Proceedings of the 2007 IEEE International SOC Conference, 2007

A Power Network Synthesis Method for Industrial Power Gating Designs.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Low Power Methodology Manual - for System-on-Chip Design.
Springer, ISBN: 978-0-387-71818-7, 2007

2006
Challenges in sleep transistor design and implementation in low-power designs.
Proceedings of the 43rd Design Automation Conference, 2006

2005
A Clock Isolation Method For Complex SoC Designs.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Virtual Hierarchical Design Representations for Distributed Optimization of Multi-Million Gate Designs.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

2003
Hybrid hierarchical timing closure methodology for a high performance and low power DSP.
Proceedings of the 40th Design Automation Conference, 2003


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