Nainesh Agarwal

According to our database1, Nainesh Agarwal authored at least 10 papers between 2004 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2017
Detecting Broad Length Algorithmically Generated Domains.
Proceedings of the Intelligent, Secure, and Dependable Systems in Distributed and Cloud Environments, 2017

2009
Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing.
Proceedings of the Embedded Computer Systems: Architectures, 2009

2008
FSMD Partitioning for Low Power Using ILP.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

FSMD partitioning for low power using simulated annealing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction.
Proceedings of the Embedded Computer Systems: Architectures, 2007

DSPstone Benchmark of CoDeL's Automated Clock Gating Platform.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Towards Automated Power Gating of Registers using CoDeL.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Efficient Automated Clock Gating Using CoDeL.
Proceedings of the Embedded Computer Systems: Architectures, 2006

Power efficient rapid hardware development using CoDel and automated clock gating.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2004
Using CoDeL to Rapidly Prototype Network Processsor Extensions.
Proceedings of the Computer Systems: Architectures, 2004


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