Nikitas J. Dimopoulos

According to our database1, Nikitas J. Dimopoulos authored at least 88 papers between 1983 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Multiobjective GPU design space exploration optimization.
Microprocessors and Microsystems - Embedded Hardware Design, 2019

Dual-Stage Phase Unwrapping.
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019

Scale Invariant Super-Resolutions Methods with Application to InSAR Images.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2017
Execution Phase Prediction Based on Phase Precursors and Locality.
Proceedings of the 5th International Workshop on Energy Efficient Supercomputing, 2017

A Study on the Effects of Lesions on CA3b in Hippocampus.
Proceedings of the Advances in Neural Networks - ISNN 2017 - 14th International Symposium, 2017

Sensitivity and similarity regularization in dynamic selection of ensembles of neural networks.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Optimum Power-Performance GPU Configuration Prediction Based on Code Attributes.
Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017

SAPPP: The Software-Aware Power and Performance Profiler.
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017

A New Approach to Detecting Execution Phases Using Performance Monitoring Counters.
Proceedings of the Architecture of Computing Systems - ARCS 2017, 2017

2015
Investigating the effects of store value locality on processor power.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2015

GPU design space exploration: NN-based models.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2015

In-training and post-training generalization methods: The case of ppar - α and ppar - γ agonists.
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015

2014
An analysis of dynamics of CA3b in Hippocampus.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

An improved RBM based on Bayesian Regularization.
Proceedings of the 2014 International Joint Conference on Neural Networks, 2014

2013
Relating Application Memory Activity to Processor Power.
Proceedings of the 42nd International Conference on Parallel Processing, 2013

2012
An improved neural network ensemble model of Aldose Reductase inhibitory activity.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012

Efficient Design Space Exploration of GPGPU Architectures.
Proceedings of the Euro-Par 2012: Parallel Processing Workshops, 2012

Using indirection to minimize message delivery latency on cache-less many-core architectures.
Proceedings of the 25th IEEE Canadian Conference on Electrical and Computer Engineering, 2012

2011
Single-port and multi-port collective communication operations on single and dual Cell BE processor systems.
IJCNDS, 2011

2009
Hiding message delivery latency using Direct-to-Cache-Transfer techniques in message passing environments.
Microprocessors and Microsystems - Embedded Hardware Design, 2009

Resource allocation on computational grids using a utility model and the knapsack problem.
Future Generation Comp. Syst., 2009

Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing.
Proceedings of the Embedded Computer Systems: Architectures, 2009

2008
FSMD Partitioning for Low Power Using ILP.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

FSMD partitioning for low power using simulated annealing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Extended characterization of DMA transfers on the Cell BE processor.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

2007
Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction.
Proceedings of the Embedded Computer Systems: Architectures, 2007

DSPstone Benchmark of CoDeL's Automated Clock Gating Platform.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Comparing Direct-to-Cache Transfer Policies to TCP/IP and M-VIA During Receive Operations in MPI Environments.
Proceedings of the Parallel and Distributed Processing and Applications, 2007

Towards Automated Power Gating of Registers using CoDeL.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Improved Grid Metascheduler Design using the Plackett-Burman Methodology.
Proceedings of the 21st Annual International Symposium on High Performance Computing Systems and Applications (HPCS 2007), 2007

Intelligent Selection of Fault Tolerance Techniques on the Grid.
Proceedings of the Third International Conference on e-Science and Grid Computing, 2007

Exploiting Task Temperature Profiling in Temperature-Aware Task Scheduling for Computational Clusters.
Proceedings of the Advances in Computer Systems Architecture, 2007

2006
Wavelet denoising of coarsely quantized signals.
IEEE Trans. Instrumentation and Measurement, 2006

Diagnosing faulty cable network segments from modem power readings.
TBC, 2006

Hiding message delivery and reducing memory access latency by providing direct-to-cache transfer during receive operations in a message passing environment.
SIGARCH Computer Architecture News, 2006

Efficient Automated Clock Gating Using CoDeL.
Proceedings of the Embedded Computer Systems: Architectures, 2006

Power efficient rapid hardware development using CoDel and automated clock gating.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Sensitivity analysis of knapsack-based task scheduling on the grid.
Proceedings of the 20th Annual International Conference on Supercomputing, 2006

Evaluation of Knapsack-Based Scheduling Using the NPACI JOBLOG.
Proceedings of the 20th Annual International Symposium on High Performance Computing Systems and Applications (HPCS 2006), 2006

Metascheduling Multiple Resource Types using the MMKP.
Proceedings of the 7th IEEE/ACM International Conference on Grid Computing (GRID 2006), 2006

Lazy direct-to-cache transfer during receive operations in a message passing environment.
Proceedings of the Third Conference on Computing Frontiers, 2006

2005
A New Heuristic for Solving the Multichoice Multidimensional Knapsack Problem.
IEEE Trans. Systems, Man, and Cybernetics, Part A, 2005

Optimal fault detection for coarsely quantized systems.
Proceedings of the IEEE International Conference on Systems, 2005

2004
Guided construction of training data set for neural networks.
Proceedings of the IEEE International Conference on Systems, 2004

CoDeL: Automatically Synthesizing Network Interface Controllers.
Proceedings of the Computer Systems: Architectures, 2004

Using CoDeL to Rapidly Prototype Network Processsor Extensions.
Proceedings of the Computer Systems: Architectures, 2004

Resource Management and Knapsack Formulations on the Grid.
Proceedings of the 5th International Workshop on Grid Computing (GRID 2004), 2004

2003
Channel resource allocation/reallocation in cellular communication and linear programming.
Proceedings of the IEEE International Conference on Systems, 2003

Topic Introduction.
Proceedings of the Euro-Par 2003. Parallel Processing, 2003

2002
Analysis of a Latency Hiding Broadcasting Algorithm on a Reconfigurable Optical Interconnect.
Parallel Processing Letters, 2002

Efficient communication using message prediction for clusters of multiprocessors.
Concurrency and Computation: Practice and Experience, 2002

Architectural Extensions to Support Efficient Communication Using Message Prediction.
Proceedings of the 16th Annual International Symposium on High Performance Computing Systems and Applications, 2002

2001
Optimal Total Exchange in Cayley Graphs.
IEEE Trans. Parallel Distrib. Syst., 2001

2000
Efficient Communication Using Message Prediction for Cluster Multiprocessors.
Proceedings of the Network-Based Parallel Computing: Communication, 2000

1999
On Broadcasting Time.
Parallel Processing Letters, 1999

Hiding Communication Latency in Reconfigurable Message-Passing Environments.
Proceedings of the 13th International Parallel Processing Symposium / 10th Symposium on Parallel and Distributed Processing (IPPS / SPDP '99), 1999

1998
A Theory for Total Exchange in Multidimensional Interconnection Networks.
IEEE Trans. Parallel Distrib. Syst., 1998

Communications Latency Hiding Techniques for a Reconfigurable Optical Interconnect: Benchmark Studies.
Proceedings of the Applied Parallel Computing, 1998

1997
Collective Communications on a Reconfigurable Optical Interconnect.
Proceedings of the On Principles Of Distributed Systems, 1997

1996
Training Asymptotically Stable Recurrent Neural Networks.
Intelligent Automation & Soft Computing, 1996

Decomposition of Total Exchange for Multidimensional Interconnects.
Proceedings of the 1996 International Conference on Parallel Processing, 1996

Leaf Communications in Complete Trees.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

Tota; Exchange in Cayley Networks.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

1995
A probabilistic approach for reducing the search cost in binary decision trees.
IEEE Trans. Systems, Man, and Cybernetics, 1995

Optimal and Suboptimal Processor Allocation for Hypercycle-based Multiprocessors.
IEEE Trans. Parallel Distrib. Syst., 1995

Timing analysis for synthesis of hardware interface controllers using timed signal transition graphs.
Proceedings of the Sixth International Workshop on Petri Nets and Performance Models, 1995

Assessing the feasibility of interface designs before their implementation.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994
Timing analysis for synthesis in microprocessor interface design.
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Optimal total exchange in linear arrays and rings.
Proceedings of the International Symposium on Parallel Architectures, 1994

1993
Recurrent neural networks in systems identification.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Identification of a PUMA-560 two-link robot using a stable neural network.
Proceedings of International Conference on Neural Networks (ICNN'88), San Francisco, CA, USA, March 28, 1993

1992
Routing in Hypercycles. Deadlock Free and Backtracking Strategies.
Proceedings of the PARLE '92: Parallel Architectures and Languages Europe, 1992

1991
Depth perception using blurring and its application in VLSI wafer probing.
Mach. Vis. Appl., 1991

Routing and processor allocation on a Hypercycle-based multiprocessor.
Proceedings of the 5th international conference on Supercomputing, 1991

1990
Learning in asymptotically behaving neural networks.
Proceedings of the IJCNN 1990, 1990

Modelling Signal Behaviour in DAME.
Proceedings of the Third International Conference on Industrial and Engineering Applications of Artificial Intelligence and Expert Systems, IEA/AIE 1990, July 15-18, 1990, The Mills House Hotel, Charleston, SC, USA, 1990

Performance Evaluation of the Backtrack-to-Origin-and-Retry Routing for Hypercycle-Based Interconnection Networks.
Proceedings of the 10th International Conference on Distributed Computing Systems (ICDCS 1990), May 28, 1990

1989
DAME: a rule based designer of microprocessor based systems.
Proceedings of the Second International Conference on Industrial & Engineering Applications of Artificial Intelligence & Expert Systems, IEA/AIE 1989, June 6-9, 1989, Tullahoma, TN, USA, 1989

1988
Collision-free protocol for local area networks.
Computer Communications, 1988

Throughput analysis of a collision free protocol for local area network.
Proceedings of the 13th Conference on Local Computer Networks, 1988

A micro-manipulator vision in IC Manufacturing.
Proceedings of the 1988 IEEE International Conference on Robotics and Automation, 1988

1987
Throughput and Packet Delay Analysis for the H-Network: CSMA/CD with Adaptive and Nonadaptive Backoff Protocols.
IEEE Trans. Communications, 1987

The HM-Nucleus: Distributed Kernel Design for the Homogeneous Multiprocessor.
IEEE Micro, 1987

MAX: Advanced General Purpose Real-Time Multicomputer for Space Applications.
Proceedings of the 8th IEEE Real-Time Systems Symposium (RTSS '87), 1987

Advanced General Purpose Multicomputer for Space Applications.
Proceedings of the International Conference on Parallel Processing, 1987

The Homogeneous Multiprocessor System, An Overview.
Proceedings of the International Conference on Parallel Processing, 1987

1985
On the Structure of the Homogeneous Multiprocessor.
IEEE Trans. Computers, 1985

1983
The Homogeneous Multiprocessor Architecture : Structure and Performance Analysis.
Proceedings of the International Conference on Parallel Processing, 1983


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