Nameun Kang

According to our database, Nameun Kang authored at least 6 papers between 2021 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

MRAM-Based Analog Computing-In-Memory Macro With Reconfigurable In-Memory Reference ADC.

Kyung Min Lee, Munhyeon Kim, Nameun Kang, Inhwan Lee, Jehun Lee, Joon Hwang, Jong-Ho Lee, Jae-Joon Kim

IEEE Access, 2026

2025

Partial-Sum Quantization Based on Pseudo-Quantization Noise for Variation-Tolerant Analog In-Memory Computing.

Nameun Kang, Eunhyeok Park, Sangsu Park, Jongil Kim, Jaeyun Yi, Jae-Joon Kim

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2025

2023

A Capacitive Computing-In-Memory Circuit With Low Input Loading SRAM Bitcell and Adjustable ADC Input Range.

Eunhwan Kim, Hyunmyung Oh, Nameun Kang, Jihoon Park, Jae-Joon Kim

IEEE Trans. Circuits Syst. II Express Briefs, September, 2023

In-Memory Neural Network Accelerator based on eDRAM Cell with Enhanced Retention Time.

Inhwan Lee, Eunhwan Kim, Nameun Kang, Hyunmyung Oh, Jae-Joon Kim

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

TAIM: ternary activation in-memory computing hardware with 6T SRAM array.

Nameun Kang, Hyungjun Kim, Hyunmyung Oh, Jae-Joon Kim

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Single RRAM Cell-based In-Memory Accelerator Architecture for Binary Neural Networks.

Hyunmyung Oh, Hyungjun Kim, Nameun Kang, Yulhwa Kim, Jihoon Park, Jae-Joon Kim

Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021