Hyunmyung Oh
Orcid: 0000-0003-1392-9364
According to our database1,
Hyunmyung Oh
authored at least 9 papers
between 2015 and 2023.
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Bibliography
2023
A Capacitive Computing-In-Memory Circuit With Low Input Loading SRAM Bitcell and Adjustable ADC Input Range.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023
In-Memory Neural Network Accelerator based on eDRAM Cell with Enhanced Retention Time.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
Maximizing Parallel Activation of Word-Lines in MRAM-Based Binary Neural Network Accelerators.
IEEE Access, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Energy-efficient charge sharing-based 8T2C SRAM in-memory accelerator for binary neural networks in 28nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
Single RRAM Cell-based In-Memory Accelerator Architecture for Binary Neural Networks.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
Energy-efficient XNOR-free In-Memory BNN Accelerator with Input Distribution Regularization.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
2015