Nan-Hsin Tseng

According to our database, Nan-Hsin Tseng authored at least 4 papers between 2011 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

Defect-Finding with Timing-Partitioned Small-Delay-Defect Methodology: Silicon Practice on N2.

Hao-Yu Yang, Hsin-Wei Hung, Nan-Hsin Tseng

Proceedings of the IEEE International Test Conference, 2025

Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion.

Cheng-En Chung, Jun-Han Jian, Kuen-Jong Lee, Nan-Hsin Tseng, Hsin-Wei Hung, Hao-Yu Yang, Dong-Yi Chen

Proceedings of the IEEE International Test Conference, 2025

2024

An On-chip High-resolution Delay Measurement Scheme for TSVs in 3DIC.

Dong-Yi Chen, Cheng-Hong Lee, Kuen-Jong Lee, Nan-Hsin Tseng, Hsin-Wei Hung, Hao-Yu Yang

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024

2011

An Accurate Timing-Aware Diagnosis Algorithm for Multiple Small Delay Defects.

Po-Juei Chen, Wei-Li Hsu, James Chien-Mo Li, Nan-Hsin Tseng, Kuo-Yin Chen, Wei-pin Changchien, Charles C. C. Liu

Proceedings of the 20th IEEE Asian Test Symposium, 2011