Wei-pin Changchien

According to our database, Wei-pin Changchien authored at least 3 papers between 2011 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

An On-Chip Current-Sink-Free Adaptive-Timing Power Impedance Measurement (PIM) Unit for 3D-IC in 5nm FinFET Technology.

Tsung-Che Lu, Chin-Ming Fu, Wei-Hsiang Wang, Fred Kuo, Chih-Hsien Chang, Kenny Hsieh, King-Ho Tam, Tze-Chiang Huang, Tom Chen, Mei Wong, Wei-pin Changchien, Frank Lee

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2013

Diagnosis and Layout Aware (DLA) scan chain stitching.

Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan

Proceedings of the 2013 IEEE International Test Conference, 2013

2011

An Accurate Timing-Aware Diagnosis Algorithm for Multiple Small Delay Defects.

Po-Juei Chen, Wei-Li Hsu, James Chien-Mo Li, Nan-Hsin Tseng, Kuo-Yin Chen, Wei-pin Changchien, Charles C. C. Liu

Proceedings of the 20th IEEE Asian Test Symposium, 2011