Chien-Mo James Li

According to our database1, Chien-Mo James Li authored at least 81 papers between 1998 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2020
Diagnosis technique for Clustered Multiple Transition Delay Faults.
Proceedings of the IEEE International Test Conference in Asia, 2020

Automatic IR-Drop ECO Using Machine Learning.
Proceedings of the IEEE International Test Conference in Asia, 2020

High Efficiency and Low Overkill Testing for Probabilistic Circuits.
Proceedings of the IEEE International Test Conference in Asia, 2020

Realistic Fault Models and Fault Simulation for Quantum Dot Quantum Circuits.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
DR-Scan: Dual-Rail Asynchronous Scan DfT and ATPG.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

ATPG and Test Compression for Probabilistic Circuits.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

2018
A new method for parameter estimation of high-order polynomial-phase signals.
Signal Process., 2018

IR drop prediction of ECO-revised circuits using machine learning.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Diagnosis and repair of cells (DRC) responsible for power-supply-noise violations.
Proceedings of the 2018 International Symposium on VLSI Design, 2018

Parallel order ATPG for test compaction.
Proceedings of the 2018 International Symposium on VLSI Design, 2018

Test methodology for PCHB/PCFB Asynchronous Circuits.
Proceedings of the IEEE International Test Conference, 2018

Machine-learning-based dynamic IR drop prediction for ECO.
Proceedings of the International Conference on Computer-Aided Design, 2018

Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
PSN-aware circuit test timing prediction using machine learning.
IET Comput. Digit. Tech., 2017

Robust test pattern generation for hold-time faults in nanometer technologies.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

Physical-aware diagnosis of multiple interconnect defects.
Proceedings of the International Test Conference in Asia, 2017

Test Methodology for Dual-rail Asynchronous Circuits.
Proceedings of the 54th Annual Design Automation Conference, 2017

Test Pattern Compression for Probabilistic Circuits.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016
Test Pattern Modification for Average IR-Drop Reduction.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A Multicircuit Simulator Based on Inverse Jacobian Matrix Reuse.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Power-Supply-Noise-Aware Timing Analysis and Test Pattern Regeneration.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

2015
TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for cell-internal defects.
Proceedings of the VLSI Design, Automation and Test, 2015

Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014
Transient IR-Drop Analysis for At-Speed Testing Using Representative Random Walk.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Physical-aware systematic multiple defect diagnosis.
IET Comput. Digit. Tech., 2014

Divide and conquer diagnosis for multiple defects.
Proceedings of the 2014 International Test Conference, 2014

GPU-based timing-aware test generation for small delay defects.
Proceedings of the 19th IEEE European Test Symposium, 2014

2013
Compact Test Pattern Selection for Small Delay Defect.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Automatic test pattern generation for delay defects using timed characteristic functions.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

GPU-based n-detect transition fault ATPG.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Test Generation of Path Delay Faults Induced by Defects in Power TSV.
Proceedings of the 22nd Asian Test Symposium, 2013

Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.
ACM Trans. Design Autom. Electr. Syst., 2012

An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis.
IEEE Trans. Computers, 2012

3D IC test scheduling using simulated annealing.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

2011
Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Row-linear feedback shift register-column x-masking technique for simultaneous testing of many-core system chips.
IET Comput. Digit. Tech., 2011

An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology.
J. Electron. Test., 2011

Placement Optimization of Flexible TFT Digital Circuits.
IEEE Des. Test Comput., 2011

Test clock domain optimization for peak power supply noise reduction during scan.
Proceedings of the 2011 IEEE International Test Conference, 2011

An at-speed self-testable technique for the high speed domino adder.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

An Accurate Timing-Aware Diagnosis Algorithm for Multiple Small Delay Defects.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-In.
IEEE Trans. Very Large Scale Integr. Syst., 2010

CSER: BISER-based concurrent soft-error resilience.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Static timing analysis for flexible TFT circuits.
Proceedings of the 47th Design Automation Conference, 2010

2009
Time-space test response compaction and diagnosis based on BCH codes.
IET Comput. Digit. Tech., 2009

Very-Low-Voltage testing of amorphous silicon TFT circuits.
Proceedings of the 2009 IEEE International Test Conference, 2009

Power scan: DFT for power switches in VLSI designs.
Proceedings of the 2009 IEEE International Test Conference, 2009

BIST design optimization for large-scale embedded memory cores.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

Bridging Fault Diagnosis to Identify the Layer of Systematic Defects.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

Fault modeling and testing of retention flip-flops in low power designs.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Effective and Economic Phase Noise Testing for Single-Chip TV Tuners.
IEEE Trans. Instrum. Meas., 2008

Diagnosis of Multiple Scan Chain Timing Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A Two-level Simultaneous Test Data and Time Reduction Technique for SOC.
J. Inf. Sci. Eng., 2008

Simultaneous capture and shift power reduction test pattern generator for scan testing.
IET Comput. Digit. Tech., 2008

Survey of Scan Chain Diagnosis.
IEEE Des. Test Comput., 2008

Diagnosis of Logic-to-chain Bridging Faults.
Proceedings of the 2008 IEEE International Test Conference, 2008

IEEE 1500 Compatible Secure Test Wrapper For Embedded IP Cores.
Proceedings of the 2008 IEEE International Test Conference, 2008

On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007
Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis.
IEEE Trans. Computers, 2007

Design and Chip Implementation of the Segment Weighted Random BIST for Low Power Testing.
J. Low Power Electron., 2007

Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Jump Simulation: A Technique for Fast and Precise Scan Chain Fault Diagnosis.
Proceedings of the 2006 IEEE International Test Conference, 2006

2005
Diagnosis of single stuck-at faults and multiple timing faults in scan chains.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Diagnosis of Multiple Hold-Time and Setup-Time Faults in Scan Chains.
IEEE Trans. Computers, 2005

Diagnosis of Timing Faults in Scan Chains Using Single Excitation Patterns.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Jump Scan: A DFT Technique for Low Power Testing.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Column parity and row selection (CPRS): a BIST diagnosis technique for multiple errors in multiple scan chains.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004
ELF-Murphy Data on Defects and Test Sets.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

2002
Diagnosis of Sequence-Dependent Chips.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

2001
Diagnosis of Tunneling Opens.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Testing for resistive opens and stuck opens.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000
Testing for tunneling opens.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1998
Analysis of pattern-dependent and timing-dependent failures in an experimental test chip.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998


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