Nandakumar Nambath

Orcid: 0000-0001-8168-0500

According to our database1, Nandakumar Nambath authored at least 14 papers between 2012 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
Performance evaluation of evolutionary algorithms for analog integrated circuit design optimisation.
Microelectron. J., November, 2023

Cascode Cross-Coupled Stage High-Speed Dynamic Comparator in 65 nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2023

Triple-Tail Common-Mode Insensitive High-Speed Dynamic Comparator for Analog In-Memory Computing Architectures.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
Area Optimisation of Two Stage Miller Compensated Op-Amp in 65 nm Using Hybrid PSO.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

2021
Cascode Cross-Coupled Stage High-Speed Dynamic Comparator in 65 nm.
CoRR, 2021

Hybrid Particle Swarm Optimization Algorithm for Area Minimization in 65 nm Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2019
Adaptive Polarization Control for Coherent Optical Links with Polarization Multiplexed Carrier.
Proceedings of the National Conference on Communications, 2019

2018
A Quadrature-Phase Voltage Controlled Oscillator for Offset Phase and Frequency Compensation.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

2017
Demonstration of a polarization diversity based SH-QPSK system with CMA-DFE equalizer.
Proceedings of the 26th Wireless and Optical Communication Conference, 2017

First demonstration of an all analog adaptive equalizer for coherent DP-QPSK links.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2017

2016
Analog domain decision feedback equalizer for repeater-less DP-QPSK coherent optical links.
Proceedings of the 25th Wireless and Optical Communication Conference, 2016

Wideband Active Delay Cell Design for Analog Domain Coherent DP-QPSK Optical Receiver.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2013
A low power 100 Gbps DP-QPSK receiver using analog domain signal processing.
Proceedings of the International Conference on Computing, Networking and Communications, 2013

2012
Analog Processing Based Equalizer for 40 Gbps Coherent Optical Links in 90 nm CMOS.
Proceedings of the 25th International Conference on VLSI Design, 2012


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