Naoyuki Yoshida

According to our database1, Naoyuki Yoshida authored at least 1 paper in 1994.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

1994
250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture.
IEEE J. Solid State Circuits, April, 1994


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