Yasuji Koshikawa

According to our database, Yasuji Koshikawa authored at least 2 papers between 1994 and 2005.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2005

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer.

Hiroki Fujisawa, Masayuki Nakamura, Yasuhiro Takai, Yasuji Koshikawa, Tatsuya Matano, Seiji Narui, Narikazu Usuki, Chiaki Dono, Shinichi Miyatake, Makoto Morino, Koji Arai, Shuichi Kubouchi, Isamu Fujii, Hideyuki Yoko, Takao Adachi

IEEE J. Solid State Circuits, 2005

1994

250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture.

Yasuhiro Takai, Mamoru Nagase, Mamoru Kitamura, Yasuji Koshikawa, Naoyuki Yoshida, Yasuaki Kobayashi, Takashi Obara, Yukio Fukuzo, Hiroshi Watanabe

IEEE J. Solid State Circuits, April, 1994