Mamoru Nagase

According to our database, Mamoru Nagase authored at least 1 paper in 1994.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1994

250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture.

Yasuhiro Takai, Mamoru Nagase, Mamoru Kitamura, Yasuji Koshikawa, Naoyuki Yoshida, Yasuaki Kobayashi, Takashi Obara, Yukio Fukuzo, Hiroshi Watanabe

IEEE J. Solid State Circuits, April, 1994