Nathalie Drach-Temam

According to our database1, Nathalie Drach-Temam
  • authored at least 28 papers between 1993 and 2016.
  • has a "Dijkstra number"2 of four.



In proceedings 
PhD thesis 





NUMA-aware scheduling and memory allocation for data-flow task-parallel applications.
Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2016

Scalable Task Parallelism for NUMA: A Uniform Abstraction for Coordinated Scheduling and Memory Management.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

Topology-Aware and Dependence-Aware Scheduling and Memory Allocation for Task-Parallel Languages.
TACO, 2014

Automatic Detection of Performance Anomalies in Task-Parallel Programs.
CoRR, 2014

An out-of-order superscalar processor on FPGA: The ReOrder Buffer design.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Low-cost recovery for the code integrity protection in secure embedded processors.
Proceedings of the HOST 2011, 2011

Using Runtime Activity to Dynamically Filter Out Inefficient Data Prefetches.
Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011

Morpheo: A high-performance processor generator for a FPGA implementation.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

Low-cost fault tolerance on the ALU in simple pipelined processors.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Étude de la sensibilité aux jeux de données de la compilation itérative.
Technique et Science Informatiques, 2008

A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs.
Proceedings of the Design, Automation and Test in Europe, 2008

Architecture optimization for multimedia application exploiting data and thread-level parallelism.
Journal of Systems Architecture, 2005

VHC: Quickly Building an Optimizer for Complex Embedded Architectures.
Proceedings of the 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 2004

Algorithme d'ordonnancement dynamique pour exécution statique.
Technique et Science Informatiques, 2003

Increasing hardware data prefetching performance using the second-level cache.
Journal of Systems Architecture, 2002

Improving 3D geometry transformations on a simultaneous multithreaded SIMD processor.
Proceedings of the 15th international conference on Supercomputing, 2001

Memory Bandwidth: The True Bottleneck of SIMD Multimedia Performance on a Superscalar Processor.
Proceedings of the Euro-Par 2001: Parallel Processing, 2001

The Best Distribution for a Parallel OpenGL 3D Engine with Texture Caches.
Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000

Two Schemes to Improve the Performance of a Sort-Last 3D Parallel Rendering Machine with Texture Caches.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

A Parallel Algorithm for 3D Geometry Transformations in OpenGL.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

Evaluation of High Performance Multicache Parallel Texture Mapping.
Proceedings of the 12th international conference on Supercomputing, 1998

About Cache Associativity in Low-Cost Shared Memory Multi-Microprocessors.
Parallel Processing Letters, 1995

Software assistance for data caches.
Future Generation Comp. Syst., 1995

Hardware Implementation Issues of Data Prefetching.
Proceedings of the 9th international conference on Supercomputing, 1995

Software Assistance for Data Caches.
Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture (HPCA 1995), 1995

Direct-mapped versus set-associative pipelined caches.
Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, 1995

MIDEE: smoothing branch and instruction cache miss penalties on deep pipelines.
Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

Semi-Unified Caches.
Proceedings of the 1993 International Conference on Parallel Processing, 1993