André Seznec

According to our database1, André Seznec authored at least 123 papers between 1986 and 2018.

Collaborative distances:

Awards

ACM Fellow

ACM Fellow 2016, "For contributions to branch prediction and cache memory design".

IEEE Fellow

IEEE Fellow 2013, "For contributions to design of branch predictors and cache memory for processor architectures".

Timeline

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PhD thesis 
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Bibliography

2018
DITVA: Dynamic Inter-Thread Vectorization Architecture.
J. Parallel Distrib. Comput., 2018

Cost effective speculation with the omnipredictor.
Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018

Synergistic cache layout for reuse and compression.
Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018

2017
Band-Pass Prefetching: An Effective Prefetch Management Mechanism Using Prefetch-Fraction Metric in Multi-Core Systems.
TACO, 2017

On the Interactions Between Value Prediction and Compiler Optimizations in the Context of EOLE.
TACO, 2017

Dynamic and discrete cache insertion policies for managing shared last level caches in large multicores.
J. Parallel Distrib. Comput., 2017

Storage-Free Memory Dependency Prediction.
Computer Architecture Letters, 2017

Compile-time function memoization.
Proceedings of the 26th International Conference on Compiler Construction, 2017

2016
EOLE: Combining Static and Dynamic Scheduling Through Value Prediction to Reduce Complexity and Increase Performance.
ACM Trans. Comput. Syst., 2016

Yet Another Compressed Cache: A Low-Cost Yet Effective Compressed Cache.
TACO, 2016

Practical Multidimensional Branch Prediction.
IEEE Micro, 2016

Dynamic Inter-Thread Vectorization Architecture: Extracting DLP from TLP.
Proceedings of the 28th International Symposium on Computer Architecture and High Performance Computing, 2016

Register sharing for equality prediction.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Dictionary sharing: An efficient cache compression scheme for compressed caches.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Discrete Cache Insertion Policies for Shared Last Level Cache Management on Large Multicores.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium, 2016

Cost effective physical register sharing.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015
Intercepting Functions for Memoization: A Case Study Using Transcendental Functions.
TACO, 2015

Revisiting Clustered Microarchitecture for Future Superscalar Cores: A Case for Wide Issue Clusters.
TACO, 2015

EOLE: Toward a Practical Implementation of Value Prediction.
IEEE Micro, 2015

BADCO: Behavioral Application-Dependent Superscalar Core Models.
International Journal of Parallel Programming, 2015

The inner most loop iteration counter: a new dimension in branch history.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

Long term parking (LTP): criticality-aware resource allocation in OOO processors.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

Cost-effective speculative scheduling in high performance processors.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

BeBoP: A cost effective predictor infrastructure for superscalar value prediction.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Prediction-based superpage-friendly TLB designs.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Sequential and Parallel Code Sections are Different: they may require different Processors.
Proceedings of the 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 4th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2015

Branch prediction and the performance of interpreters: don't trust folklore.
Proceedings of the 13th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2015

An empirical high level performance model for future many-cores.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

2014
Efficient Out-of-Order Execution of Guarded ISAs.
TACO, 2014

Hardware/Software Helper Thread Prefetching on Heterogeneous Many Cores.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

Impact of Serial Scaling of Multi-threaded Programs in Many-Core Era.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing Workshop, 2014

Skewed Compressed Caches.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

EOLE: Paving the way for an effective implementation of value prediction.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Practical data value speculation for future high-end processors.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013
Faster unicores are still needed.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

Selecting benchmark combinations for the evaluation of multicore throughput.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

Performance upper bound analysis and optimization of SGEMM on Fermi and Kepler GPUs.
Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization, 2013

Message from the program chairs.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012
SYRANT: SYmmetric resource allocation on not-taken and taken paths.
TACO, 2012

BADCO: Behavioral Application-Dependent Superscalar Core model.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

PRETI: partitioned real-time shared cache for mixed-criticality real-time systems.
Proceedings of the 20th International Conference on Real-Time and Network Systems, 2012

Break down GPU execution time with an analytical method.
Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2012

2011
Branch Predictors.
Proceedings of the Encyclopedia of Parallel Computing, 2011

Managing SMT resource usage through speculative instruction window weighting.
TACO, 2011

Fairness Metrics for Multi-Threaded Processors.
Computer Architecture Letters, 2011

A new case for the TAGE branch predictor.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

Storage free confidence estimation for the TAGE branch predictor.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

Practical and secure PCM systems by online detection of malicious write streams.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

Decoupled zero-compressed memory.
Proceedings of the High Performance Embedded Architectures and Compilers, 2011

2010
A Phase Change Memory as a Secure Main Memory.
Computer Architecture Letters, 2010

Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses.
Proceedings of the 7th Conference on Computing Frontiers, 2010

2009
Fetch Gating Control through Speculative Instruction Window Weighting.
Trans. HiPEAC, 2009

Parallel HAVEGE.
Proceedings of the Parallel Processing and Applied Mathematics, 2009

Zero-content augmented caches.
Proceedings of the 23rd international conference on Supercomputing, 2009

2008
Speculative return address stack management revisited.
TACO, 2008

2007
High-Performance Embedded Architecture and Compilation Roadmap.
Trans. HiPEAC, 2007

A study of thread migration in temperature-constrained multicores.
TACO, 2007

The Idealistic GTL Predictor.
J. Instruction-Level Parallelism, 2007

The L-TAGE Branch Predictor.
J. Instruction-Level Parallelism, 2007

Fetch Gating Control Through Speculative Instruction Window Weighting.
Proceedings of the High Performance Embedded Architectures and Compilers, 2007

Exploiting Single-Usage for Effective Memory Management.
Proceedings of the Advances in Computer Systems Architecture, 2007

2006
A case for a complexity-effective, width-partitioned microarchitecture.
TACO, 2006

A case for (partially) TAgged GEometric history length branch prediction.
J. Instruction-Level Parallelism, 2006

2005
Conflict-Free Accesses to Strided Vectors on a Banked Cache.
IEEE Trans. Computers, 2005

Performance implications of single thread migration on a chip multi-core.
SIGARCH Computer Architecture News, 2005

The strict avalanche criterion randomness test.
Mathematics and Computers in Simulation, 2005

Genesis of the O-GEHL Branch Predictor.
J. Instruction-Level Parallelism, 2005

Analysis of the O-GEometric History Length Branch Predictor.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

2004
Concurrent Support of Multiple Page Sizes on a Skewed Associative TLB.
IEEE Trans. Computers, 2004

CASH: Revisiting Hardware Sharing in Single-Chip Parallel Processors.
J. Instruction-Level Parallelism, 2004

IATO: A Flexible EPIC Simulation Environment.
Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 2004

Speculative software management of datapath-width for energy optimization.
Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, 2004

The SAC Test: A New Randomness Test, with Some Applications to PRNG Analysis.
Proceedings of the Computational Science and Its Applications, 2004

Topic 8: Parallel Computer Architecture and Instruction-Level Parallelism.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

On the design of state-of-the-art pseudorandom number generators by means of genetic programming.
Proceedings of the IEEE Congress on Evolutionary Computation, 2004

2003
HAVEGE: A user-level software heuristic for generating empirically strong random numbers.
ACM Trans. Model. Comput. Simul., 2003

Effective ahead Pipelining of Instruction Block Address Generation.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

2002
Register write specialization register read specialization: a path to complexity-effective wide-issue superscalar processors.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor.
Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002

Tarantula: A Vector Extension to the Alpha Architecture.
Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002

2001
An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors.
International Journal of Parallel Programming, 2001

Boosting SMT Performance by Speculation Control.
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors.
Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

Topic 08+13: Instruction-Level Parallelism and Computer Architecture.
Proceedings of the Euro-Par 2001: Parallel Processing, 2001

2000
Handling Global Constraints in Compiler Strategy.
International Journal of Parallel Programming, 2000

Combining Light Static Code Annotation and Instruction-Set Emulation for Flexible and Efficient On-the-Fly Simulation (Research Note).
Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000

1999
Out-of-Order Execution may not be Cost-Effective on Processors Featuring Simultaneous Multithreading.
Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999

Code Cloning Tracing: A "Pay per Trace" Approach.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

OCEANS - Optimising Compilers for Embedded Applications.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors.
Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, 1999

1998

Improving Cache Behavior of Dynamically Allocated Data Structures.
Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, 1998

1997
Decoupled Sectored Caches.
IEEE Trans. Computers, 1997

Skewed Associativity Improves Program Performance and Enhances Predictability.
IEEE Trans. Computers, 1997

Trading Conflict and Capacity Aliasing in Conditional Branch Predictors.
Proceedings of the 24th International Symposium on Computer Architecture, 1997


1996
Don't Use the Page Number, But a Pointer To It.
Proceedings of the 23rd Annual International Symposium on Computer Architecture, 1996

Multiple-Block Ahead Branch Predictors.
Proceedings of the ASPLOS-VII Proceedings, 1996

Branch prediction and simultaneous multithreading.
Proceedings of the Fifth International Conference on Parallel Architectures and Compilation Techniques, 1996

1995
About Cache Associativity in Low-Cost Shared Memory Multi-Microprocessors.
Parallel Processing Letters, 1995

Odd Memory Systems: A New Approach.
J. Parallel Distrib. Comput., 1995

Skewed Associativity Enhances Performance Predictability.
Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995

DASC Cache.
Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture (HPCA 1995), 1995

Direct-mapped versus set-associative pipelined caches.
Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, 1995

1994
Interleaved Parallel Schemes.
IEEE Trans. Parallel Distrib. Syst., 1994

Decoupled Sectored Caches: Conciliating Low Tag Implementation Cost and Low Miss Ratio.
Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, 1994

1993
Skewed-associative Caches.
Proceedings of the PARLE '93, 1993

MIDEE: smoothing branch and instruction cache miss penalties on deep pipelines.
Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

Odd Memory Systems May be Quite Interesting.
Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993

A Case for Two-Way Skewed-Associative Caches.
Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993

Semi-Unified Caches.
Proceedings of the 1993 International Conference on Parallel Processing, 1993

About Set and Skewed Associativity on Second-Level Caches.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1992
Controlling and sequencing a heavily pipelined floating-point operator.
Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

Interleaved Parallel Schemes: Improving Memory Throughput on Supercomputers.
Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992

OPAC: A floating-point coprocessor dedicated to compute-bound kernels.
Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992

1989
A asynchronous buffering network for tightly coupled multiprocessors.
Proceedings of the 3rd international conference on Supercomputing, 1989

1988
Synchronizing Processors Through Memory Requests in a Tightly Coupled Multiprocessor.
Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988

Towards a large number of pipeline processors in a tightly coupled multiprocessor using no cache.
Proceedings of the 2nd international conference on Supercomputing, 1988

1987
A New Interconnection Network for SIMD Computers: The Sigma Network.
IEEE Trans. Computers, 1987

Optimizing Memory Throughput In a Tightly Coupled Multiprocessor.
Proceedings of the International Conference on Parallel Processing, 1987

1986
Data Synchronized Pipeline Architecture: Pipelining in Multiprocessor Environments.
J. Parallel Distrib. Comput., 1986

An Efficient Routing Control Unit for the SIGMA Network E(4).
Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, 1986

Data Synchronized Pipeline Architecture: Pipelining in Multiprocessor Environments.
Proceedings of the International Conference on Parallel Processing, 1986


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