Nattawut Thepayasuwan

According to our database1, Nattawut Thepayasuwan authored at least 9 papers between 2002 and 2005.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2005
Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Communication subsystem synthesis and analysis tool using bus architecture generation and stochastic arbitration policies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A continuous time markov decision process based on-chip buffer allocation methodology.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004
OSIRIS: Automated Synthesis of Flat and Hierarchical Bus Architectures for Deep Submicron Systems on Chip.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Hardware-Software Co-Design of Resource Constrained Systems on a Chip.
Proceedings of the 24th International Conference on Distributed Computing Systems Workshops (ICDCS 2004 Workshops), 2004

Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip.
Proceedings of the 2004 Design, 2004

2003
An exploration-based binding and scheduling technique for synthesis of digital blocks for mixed-signal applications.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

2002
A Methodology for Core Placement and Bus Synthesis under Time, Area and Energy Consumption Constraints.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002


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