Alex Doboli
Orcid: 0000-0003-2472-4014Affiliations:
- Stony Brook University, USA
According to our database1,
Alex Doboli
authored at least 133 papers
between 1994 and 2024.
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Bibliography
2024
Proceedings of the 14th IEEE Annual Computing and Communication Workshop and Conference, 2024
2023
Understanding the Significance of Mid-Tier Research Teams in Idea Flow Through a Community.
IEEE Trans. Comput. Soc. Syst., December, 2023
A Large Language Model-based Computational Approach to Improve Identity-Related Write-Ups.
CoRR, 2023
A Novel Model for Capturing the Multiple Representations during Team Problem Solving based on Verbal Discussions.
CoRR, 2023
Inching Towards Automated Understanding of the Meaning of Art: An Application to Computational Analysis of Mondrian's Artwork.
CoRR, 2023
Towards a Talking Tiny Cognitive Architecture for the Study of Spoken Language Evolution.
Proceedings of the 27th International Conference on System Theory, Control and Computing, 2023
2022
Combining informetrics and trend analysis to understand past and current directions in electronic design automation.
Scientometrics, 2022
Dynamic Diagnosis of the Progress and Shortcomings of Student Learning using Machine Learning based on Cognitive, Social, and Emotional Features.
CoRR, 2022
How Deep is Your Art: An Experimental Study on the Limits of Artistic Understanding in a Single-Task, Single-Modality Neural Network.
CoRR, 2022
Applications of diaLogic System in Individual and Team-based Problem-Solving Applications.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
Towards Insightful Automated Dialog for Therapy through Top-down/Bottom-up Response Generation.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
2021
Bottom-Up Modeling of Design Knowledge Evolution: Application to Circuit Design Community Characterization.
IEEE Trans. Comput. Soc. Syst., 2021
A novel agent-based, evolutionary model for expressing the dynamics of creative open-problem solving in small groups.
Appl. Intell., 2021
Proceedings of the IEEE International Systems Conference, 2021
A Novel Learning and Response Generating Agent-based Model for Symbolic - Numeric Knowledge Modeling and Combination.
Proceedings of the IEEE Symposium Series on Computational Intelligence, 2021
2020
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
2018
InnovA: A Cognitive Architecture for Computational Innovation Through Robust Divergence and Its Application for Analog Circuit Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Cities of the Future: Employing Wireless Sensor Networks for Efficient Decision Making in Complex Environments.
CoRR, 2018
Integrated System for Malicious Node Discovery and Self-destruction in Wireless Sensor Networks.
CoRR, 2018
2016
Moving beyond traditional electronic design automation: Data-driven design of analog circuits.
Proceedings of the 13th International Conference on Synthesis, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Analog circuit topological feature extraction with unsupervised learning of new sub-structures.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Analog Circuit Design Knowledge Mining: Discovering Topological Similarities and Uncovering Design Reasoning Strategies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Modeling semantic knowledge structures for creative problem solving: Studies on expressing concepts, categories, associations, goals and context.
Knowl. Based Syst., 2015
A low-voltage, low-power amplifier created by reasoning-based, systematic topology synthesis.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015
Optimized local control strategy for voice-based interaction-tracking badges for social applications.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Knowledge-intensive, causal reasoning for analog circuit topology synthesis in emergent and innovative applications.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Linear Programming-Based Optimization for Robust Data Modeling in a Distributed Sensing Platform.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Analog circuit design space description based on ordered clustering of feature uniqueness and similarity.
Integr., 2014
Proceedings of the 2014 IEEE International Symposium on Robotic and Sensors Environments, 2014
Novel circuit topology synthesis method using circuit feature mining and symbolic comparison.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Symbolic Matching and Constraint Generation for Systematic Comparison of Analog Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
An axiomatic model for concept structure description and its application to circuit design.
Knowl. Based Syst., 2013
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
Proceedings of the 2013 Forum on specification and Design Languages, 2013
2012
A goal-oriented programming framework for grid sensor networks with reconfigurable embedded nodes.
ACM Trans. Embed. Comput. Syst., 2012
Systematic comparison of two low-voltage amplifiers using topology matching and performance constraints.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
Decentralized detection and tracking of emergent kinetic data for wireless grids of embedded sensors.
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012
2011
Stochastic Model-Based Heuristics for Fast Field of View Loss Recovery in Urban Traffic Management Through Networks of Video Cameras.
IEEE Trans. Intell. Transp. Syst., 2011
Microelectron. J., 2011
Integr., 2011
A symbolic technique for automated characterization of the uniqueness and similarity of analog circuit design features.
Proceedings of the Design, Automation and Test in Europe, 2011
Maximizing the accuracy of sound based tracking via a low-cost network of reconfigurable embedded nodes.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011
2010
Dependable distributed data acquisition through groups of agents operating autonomously.
Proceedings of the 2010 IEEE International Workshop on Robotic and Sensors Environments, 2010
Improved sound-based localization through a network of reconfigurable mixed-signal nodes.
Proceedings of the 2010 IEEE International Workshop on Robotic and Sensors Environments, 2010
UML support for optimizing the goals of distributed control in traffic management applications.
Proceedings of the 2010 IEEE International Workshop on Robotic and Sensors Environments, 2010
Linear programming approach for performance-driven data aggregation in networks of embedded sensors.
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Reconfigurable DeltaSigma modulator topology design through hierarchical mapping and constraint extraction.
Integr., 2009
Self-destruction Procedure for Cluster-tree Wireless Sensor Networks.
Proceedings of the WINSYS 2009, 2009
Proceedings of the 5th International Symposium on Applied Computational Intelligence and Informatics, 2009
Proceedings of the 29th IEEE International Conference on Distributed Computing Systems Workshops (ICDCS 2009 Workshops), 2009
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009
Online adaptation policy design for grid sensor networks with reconfigurable embedded nodes.
Proceedings of the Design, Automation and Test in Europe, 2009
Location-Aware, Flexible Task Management for Collaborating Unmanned Autonomous Vehicles.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009
2008
Structural Macromodeling of Analog Circuits Through Model Decoupling and Transformation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
A scalable sigma-space based methodology for modeling process parameter variations in analog circuits.
Microelectron. J., 2008
Towards a model and specification for visual programming of massively distributed embedded systems.
Proceedings of the 2008 International Workshop on Robotic and Sensors Environments, 2008
Dynamic Reconfiguration of Mixed-Domain Embedded Systems for Applications with Variable Performance Requirements.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008
2007
Customization of Arbitration Policies and Buffer Space Distribution Using Continuous-Time Markov Decision Processes.
IEEE Trans. Very Large Scale Integr. Syst., 2007
Systematic Methodology for Designing Reconfigurable DeltaSigma Modulator Topologies for Multimode Communication Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Compiled code simulation of analog and mixed-signal systems using piecewise linear modeling of nonlinear parameters: A case study for DeltaSigma modulator simulation.
Integr., 2007
Knowledge based System for Reliable Perimeter Protection using Sensor Networks.
Proceedings of the WINSYS 2007, 2007
Proceedings of the 4th International Symposium on Applied Computational Intelligence and Informatics, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
SoC Design Point Selection for Dynamic Adaptation under Continuously Varying Throughput Constraints.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007
2006
Refinement-based synthesis of continuous-time analog filters through successive domain pruning, plateau search, and adaptive sampling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
High-level synthesis of ΔΣ Modulator topologies optimized for complexity, sensitivity, and power consumption.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Hierarchical constraint transformation based on genetic optimization for analog system synthesis.
Integr., 2006
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
Library of structural analog cell macromodels for design of continuous-time reconfigurable Delta Sigma modulators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
ALAMO: an improved alpha-space based methodology for modeling process parameter variations in analog circuits.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Systematic methodology for designing reconfigurable Delta-Sigma modulator topologies for multimode communication systems.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Systematic development of nonlinear analog circuit macromodels through successive operator composition and nonlinear model decoupling.
Proceedings of the 43rd Design Automation Conference, 2006
2005
Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed.
IEEE Trans. Very Large Scale Integr. Syst., 2005
Design study of (2 x 2) core architecture for matrix multiplications via programmable graph architecture.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005
An explorative tile-based technique for automated constraint transformation, placement and routing of high frequency analog filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Communication subsystem synthesis and analysis tool using bus architecture generation and stochastic arbitration policies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
A continuous time markov decision process based on-chip buffer allocation methodology.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power Consumption.
Proceedings of the 2005 Design, 2005
Buffer Insertion for Bridges and Optimal Buffer Sizing for Communication Sub-System of Systems-on-Chip.
Proceedings of the 2005 Design, 2005
Systematic development of analog circuit structural macromodels through behavioral model decoupling.
Proceedings of the 42nd Design Automation Conference, 2005
Energy conscious online architecture adaptation for varying latency constraints in sensor network applications.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005
2004
A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications.
ACM Trans. Design Autom. Electr. Syst., 2004
Proceedings of the 10th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2004), 2004
OSIRIS: Automated Synthesis of Flat and Hierarchical Bus Architectures for Deep Submicron Systems on Chip.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004
Stochastic Modeling Based Environment for Synthesis and Comparison of Bus Arbitration Policies.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004
Fast time-domain symbolic simulation for synthesis of sigma-delta analog-digital converters.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 24th International Conference on Distributed Computing Systems Workshops (ICDCS 2004 Workshops), 2004
SystemC Simulation of Continuous-Time $Sigma-Delta$ Analog-Digital Converters in the Presence of Non-linearities.
Proceedings of the Forum on specification and Design Languages, 2004
Proceedings of the 2004 Design, 2004
2003
Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
Applying Stochastic Modeling to Bus Arbitration for Network-On-Chip Systems.
Proceedings of the International Conference on VLSI, 2003
Layout-Aware Analog System Synthesis Based on Symbolic Layout Description and Combined Block Parameter Exploration, Placement and Global Routing.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003
An exploration-based binding and scheduling technique for synthesis of digital blocks for mixed-signal applications.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Synthesis of continuous-time filters and analog to digital converters by integrated constraint transformation, floorplanning and routing.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003
Towards High-Level Synthesis of Analog and Mixed-Signal Systems from VHDL-AMS Specifications.
Proceedings of the Forum on specification and Design Languages, 2003
Extraction of Piecewise-Linear Analog Circuit Models from Trained Neural Networks Using Hidden Neuron Clustering.
Proceedings of the 2003 Design, 2003
2002
A Methodology for Core Placement and Bus Synthesis under Time, Area and Energy Consumption Constraints.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Layout-Aware Synthesis Methodology for Analog Systems Based on Combined Block Sizing, Floorplanning and Global Routing.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Proceedings of the 2002 Design, 2002
2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
A regularity-based hierarchical symbolic analysis method for large-scale analog networks.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Integrated hardware-software co-synthesis for design of embedded systems under power and latency constraints.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Integrated High-Level Synthesis and Power-Net Routing for Digital Design under Switching Noise Constraints.
Proceedings of the 38th Design Automation Conference, 2001
2000
IEEE Trans. Very Large Scale Integr. Syst., 2000
A heuristic technique for system-level architecture generation from signal-flow graph representations of analog systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Towards a Specification Notation for High-Level Synthesis of Mixed-Signal and Analog Systems.
Proceedings of the 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation, 2000
1999
A Decomposition-based Symbolic Analysis Method for Analog Synthesis from Behavioral Specifications.
Proceedings of the VLSI: Systems on a Chip, 1999
A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems.
Proceedings of the 1999 Design, 1999
Proceedings of the 36th Conference on Design Automation, 1999
1998
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems.
Proceedings of the 24th EUROMICRO '98 Conference, 1998
Proceedings of the 1998 Design, 1998
1997
J. Syst. Archit., 1997
System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search.
Des. Autom. Embed. Syst., 1997
1996
Proceedings of the 9th International Symposium on System Synthesis, 1996
Proceedings of the conference on European design automation, 1996
1995
Proceedings of the Proceedings EURO-DAC'95, 1995
1994
VHDL system-level specification and partitioning in a hardware/software co-synthesis environment.
Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994