Naveen Kadayinti

According to our database, Naveen Kadayinti authored at least 9 papers between 2015 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

A True Time Delay Element using Cascaded Variable Bandwidth All Pass Filters.

Mayur S. Marinaik, Ganga K. Maheshwarappa, Naveen Kadayinti

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2018

Measurements of the effect of jitter on the performance of clock retiming circuits for on-chip interconnects.

Naveen Kadayinti, Maryam Shojaei Baghini, Dinesh Kumar Sharma

Microelectron. J., 2018

2017

Sense amplifier comparator with offset correction for decision feedback equalization based receivers.

Naveen Kadayinti, Dinesh Kumar Sharma

Microelectron. J., 2017

Clock Skew Measurement Using an All-Digital Sigma-Delta Time to Digital Converter.

Mahadev Govind Shirwaikar, Naveen Kadayinti, Dinesh Kumar Sharma

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

A Clock Retiming Circuit for Repeaterless Low Swing On-Chip Interconnects.

Naveen Kadayinti, Maryam Shojaei Baghini, Dinesh Kumar Sharma

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Settling time of mesochronous clock re-timing circuits in the presence of timing jitter.

Naveen Kadayinti, Amitalok J. Budkuley, Dinesh Kumar Sharma

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Settling Time of Mesochronous Clock Retiming Circuits for Low Swing Interconnects.

Naveen Kadayinti, Amitalok J. Budkuley, Dinesh Kumar Sharma

CoRR, 2016

2015

Testable Design of Repeaterless Low Swing On-Chip Interconnect.

Naveen Kadayinti, Dinesh Kumar Sharma

CoRR, 2015

A Clock Synchronizer for Repeaterless Low Swing On-Chip Links.

Naveen Kadayinti, Maryam Shojaei Baghini, Dinesh Kumar Sharma

CoRR, 2015