Nele Reynders

According to our database1, Nele Reynders authored at least 6 papers between 2011 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2014
27.3 A 210mV 5MHz variation-resilient near-threshold JPEG encoder in 40nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Ultra-low voltage datapath blocks in 28nm UTBB FD-SOI.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2012
Variation-Resilient Building Blocks for Ultra-Low-Energy Sub-Threshold Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Design of a 150 mV Supply, 2 MIPS, 90nm CMOS, Ultra-Low-Power Microprocessor.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

Variation-resilient sub-threshold circuit solutions for ultra-low-power Digital Signal Processors with 10MHz clock frequency.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
A 190mV supply, 10MHz, 90nm CMOS, pipelined sub-threshold adder using variation-resilient circuit techniques.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011


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