Pieter Weckx

According to our database1, Pieter Weckx authored at least 43 papers between 2012 and 2020.

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Bibliography

2020
Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Fast & Accurate Methodology for Aging Incorporation in Circuits using Adaptive Waveform Splitting (AWS).
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

eSRAM Reliability: Why is it still not optimally solved?
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

Mitigation of Sense Amplifier Degradation Using Skewed Design.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Understanding the Impact of Time-Dependent Random Variability on Analog ICs: From Single Transistor Measurements to Circuit Simulations.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Hardware-Based Aging Mitigation Scheme for Memory Address Decoder.
Proceedings of the 24th IEEE European Test Symposium, 2019

Methodology for Application-Dependent Degradation Analysis of Memory Timing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Comphy - A compact-physics framework for unified modeling of BTI.
Microelectron. Reliab., 2018

A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability.
Microelectron. Reliab., 2018

Impact and mitigation of SRAM read path aging.
Microelectron. Reliab., 2018

Self-heating-aware CMOS reliability characterization using degradation maps.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

Device aging: A reliability and security concern.
Proceedings of the 23rd IEEE European Test Symposium, 2018

Scaling CMOS beyond Si FinFET: an analog/RF perspective.
Proceedings of the 48th European Solid-State Device Research Conference, 2018

Degradation analysis of high performance 14nm FinFET SRAM.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Impact and Mitigation of Sense Amplifier Aging Degradation Using Realistic Workloads.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Dedicated technology threshold voltage tuning for 6T SRAM beyond N7.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

Mitigation of sense amplifier degradation using input switching.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Accuracy of Quasi-Monte Carlo technique in failure probability estimations.
Proceedings of the International Conference on IC Design and Technology, 2016

Capturing True Workload Dependency of BTI-induced Degradation in CPU Components.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Read path degradation analysis in SRAM.
Proceedings of the 21th IEEE European Test Symposium, 2016

Comparative BTI analysis for various sense amplifier designs.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015
Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes.
Microprocess. Microsystems, 2015

Integral impact of BTI and voltage temperature variation on SRAM sense amplifier.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Characterization of time-dependent variability using 32k transistor arrays in an advanced HK/MG technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Origins and implications of increased channel hot carrier variability in nFinFETs.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

BTI analysis of SRAM write driver.
Proceedings of the 10th International Design & Test Symposium, 2015

Impact of time-dependent variability on the yield and performance of 6T SRAM cells in an advanced HK/MG technology.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Impact of random telegraph noise on ring oscillators evaluated by circuit-level simulations.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

The defect-centric perspective of device and circuit reliability - From individual defects to circuits.
Proceedings of the 45th European Solid State Device Research Conference, 2015

Statistical simulations of 6T-SRAM cell ageing using a reliability aware simulation flow.
Proceedings of the 45th European Solid State Device Research Conference, 2015

Experimental evidences and simulations of trap generation along a percolation path.
Proceedings of the 45th European Solid State Device Research Conference, 2015

Comparative analysis of RD and Atomistic trap-based BTI models on SRAM Sense Amplifier.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Characterization and simulation methodology for time-dependent variability in advanced technologies.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
On reliability enhancement using adaptive core voltage scaling and variations on nanoscale FPGAs.
Proceedings of the 15th Latin American Test Workshop, 2014

Degradation analysis of datapath logic subblocks under NBTI aging in FinFET technology.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

NBTI Aging on 32-Bit Adders in the Downscaling Planar FET Technology Nodes.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013
Impact of duty factor, stress stimuli, gate and drive strength on gate delay degradation with an atomistic trap-based BTI model.
Microprocess. Microsystems, 2013

2012
Design of a 150 mV Supply, 2 MIPS, 90nm CMOS, Ultra-Low-Power Microprocessor.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

Impact of Duty Factor, Stress Stimuli, and Gate Drive Strength on Gate Delay Degradation with an Atomistic Trap-Based BTI Model.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012


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