Wim Dehaene

According to our database1, Wim Dehaene authored at least 164 papers between 2003 and 2020.

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Bibliography

2020
A 5-GS/s 7.2-ENOB Time-Interleaved VCO-Based ADC Achieving 30.5 fJ/cs.
IEEE J. Solid State Circuits, 2020

2019
Security on Plastics: Fake or Real?
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

Enabling Ultrasound In-Body Communication: FIR Channel Models and QAM Experiments.
IEEE Trans. Biomed. Circuits Syst., 2019

Introduction to the Special Issue on the 2018 International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2019

Memory Solutions for Flexible Thin-Film Logic: up to 8kb, >105.9kb/s LPROM and SRAM with Integrated Timing Generation Meeting the ISO NFC Standard.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 5GS/s 7.2 ENOB Time-Interleaved VCO-Based ADC Achieving 30.5fJ/conv-step.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Low Voltage Transient RESET Kinetic Modeling of OxRRAM for Neuromorphic Applications.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Dual-gate self-aligned a-InGaZnO transistor model for flexible circuit applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Ultrasound In-Body Communication with OFDM through Multipath Realistic Channels.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

2018
Impact and mitigation of SRAM read path aging.
Microelectron. Reliab., 2018

Margin Elimination Through Timing Error Detection in a Near-Threshold Enabled 32-bit Microcontroller in 40-nm CMOS.
IEEE J. Solid State Circuits, 2018

Toward Temperature Tracking With Unipolar Metal-Oxide Thin-Film SAR C-2C ADC on Plastic.
IEEE J. Solid State Circuits, 2018

STEM education in Flanders: Literacy and a positive attitude towards STEM.
IEEE Instrum. Meas. Mag., 2018

A Systematic Performance Comparison of Ultra Low-Power AES S-Boxes.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Analytic variability study of inference accuracy in RRAM arrays with a binary tree winner-take-all circuit for neuromorphic applications.
Proceedings of the 48th European Solid-State Device Research Conference, 2018

A sub 10 pJ/Cycle Over a 2 to 200 MHz Performance Range RISC- V Microprocessor in 28 nm FDSOI.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

In-Panel 31.17dB 140kHz 87µW Unipolar Dual-Gate In-Ga-Zn-O Charge-Sense Amplifier for 500dpi Sensor Array on Flexible Displays.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2017
A Smaller, Faster, and More Energy-Efficient Complementary STT-MRAM Cell Uses Three Transistors and a Ground Grid: More Is Actually Less.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A Thin-Film, a-IGZO, 128b SRAM and LPROM Matrix With Integrated Periphery on Flexible Foil.
IEEE J. Solid State Circuits, 2017

A Differential Transmission Gate Design Flow for Minimum Energy Sub-10-pJ/Cycle ARM Cortex-M0 MCUs.
IEEE J. Solid State Circuits, 2017

Introduction to the Special Issue on the 46th European Solid-State Circuits Conference (ESSCIRC).
IEEE J. Solid State Circuits, 2017

Multidisciplinary Learning through Implementation of the DVB-S2 Standard.
IEEE Commun. Mag., 2017

An 8-11b 320kS/s resolution scalable noise shaping SAR ADC.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

15.2 A flexible ISO14443-A compliant 7.5mW 128b metal-oxide NFC barcode tag with direct clock division circuit from 13.56MHz carrier.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

14.5 Envision: A 0.26-to-10TOPS/W subword-parallel dynamic-voltage-accuracy-frequency-scalable Convolutional Neural Network processor in 28nm FDSOI.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Dedicated technology threshold voltage tuning for 6T SRAM beyond N7.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

Massive MIMO processing at the semiconductor edge: Exploiting the system and circuit margins for power savings.
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

Material selection and device design guidelines for two-dimensional materials based TFETs.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

Design margin elimination in a near-threshold timing error masking-aware 32-bit ARM Cortex M0 in 40nm CMOS.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

DVAFS: Trading computational accuracy for energy through dynamic-voltage-accuracy-frequency-scaling.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Mitigation of sense amplifier degradation using input switching.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Flexible selfbiased 66.7nJ/c.s. 6bit 26S/s successive-approximation C-2C ADC with offset cancellation using unipolar Metal-Oxide TFTs.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

16.5 A flexible thin-film pixel array with a charge-to-current gain of 59µA/pC and 0.33% nonlinearity and a cost effective readout circuit for large-area X-ray imaging.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

SC1: Circuits for the internet of everything.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Iterating Von Neumann's post-processing under hardware constraints.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

Read path degradation analysis in SRAM.
Proceedings of the 21th IEEE European Test Symposium, 2016

A 16.07pJ/cycle 31MHz fully differential transmission gate logic ARM Cortex M0 core in 40nm CMOS.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

Effect of material parameters on two-dimensional materials based TFETs: An energy-delay perspective.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

TOTAL: TRNG on-the-fly testing for attack detection using Lightweight hardware.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A 28 nm CMOS 7.04 Gsps polar digital front-end processor for 60 GHz transmitter.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
Development of an Ultralow-Power Injection-Locked PSK Receiver Architecture.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A mm-Precise 60 GHz Transmitter in 40 nm CMOS for Discrete-Carrier Indoor Localization.
IEEE J. Solid State Circuits, 2015

STT-MRAM cell design with partial source line planes: improving the trade-off between area and series resistance.
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015

SC1: Circuit design in advanced CMOS technologies: How to design with lower supply voltages.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Multi-standard wideband OFDM RF-PWM transmitter in 40nm CMOS.
Proceedings of the ESSCIRC Conference 2015, 2015

Case study on the differences between EMI resilience of analog ICs against continuous wave, modulated and transient disturbances.
Proceedings of the 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits, 2015

Embedded HW/SW platform for on-the-fly testing of true random number generators.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Impact of interconnect multiple-patterning variability on SRAMs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Highly efficient entropy extraction for true random number generators on FPGAs.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Transient Behavior and Phase Noise Performance of Pulsed-Harmonic Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Frequency-Domain Analysis of Digital PWM-Based RF Modulators for Flexible Wireless Transmitters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

An MLS-Prony implementation for a cm-Precise Super 10 m range 802.15.3c-PHY 60 GHz positioning application.
J. Ambient Intell. Humaniz. Comput., 2014

Impact of multipath fading on a precise 60 GHz indoor locationing system.
Proceedings of the 2014 22nd Signal Processing and Communications Applications Conference (SIU), 2014

27.3 A 210mV 5MHz variation-resilient near-threshold JPEG encoder in 40nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

20.1 A 40nm CMOS receiver for 60GHz discrete-carrier indoor localization achieving mm-precision at 4m range.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

30.1 8b Thin-film microprocessor using a hybrid oxide-organic complementary technology with inkjet-printed P<sup>2</sup>ROM memory.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Design of a frequency reference based on a PVT-independent transmission line delay.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Modelling and mitigation of time-zero variability in sub-16nm finfet-based STT-MRAM memories.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

A 128∶2048/1536 point FFT hardware implementation with output pruning.
Proceedings of the 22nd European Signal Processing Conference, 2014

A 60GHz transmitter in 40nm CMOS achieving mm-precision for discrete-carrier localization.
Proceedings of the ESSCIRC 2014, 2014

Ultra-low voltage datapath blocks in 28nm UTBB FD-SOI.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
Teaching HW/SW Co-Design With a Public Key Cryptography Application.
IEEE Trans. Educ., 2013

Presilicon Circuit-Aware Linear Least Squares Spectral Analysis for Time-Based Data Converters.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

Joint Estimation of Propagation Delay Dispersion and Time of Arrival in a 40-nm CMOS Comparator Bank for Time-Based Receivers.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

Supply-Noise-Resilient Design of a BBPLL-Based Force-Balanced Wheatstone Bridge Interface in 130-nm CMOS.
IEEE J. Solid State Circuits, 2013

Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2013

A method for using sub-Nyquist sampling for ultra low-power positioning systems.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Session 24 overview: Energy-aware digital design.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013


Memristor-Based (ReRAM) Data Memory Architecture in ASIP Design.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

A low-power and low-voltage BBPLL-based sensor interface in 130nm CMOS for wireless sensor networks.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Fully Integrated CMOS EME-Suppressing Current Regulator for Automotive Electronics.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Variation-Resilient Building Blocks for Ultra-Low-Energy Sub-Threshold Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

A CMOS Burst-Mode Transmitter With Watt-Level RF PA and Flexible Fully Digital Front-End.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Trades-off between lithography line edge roughness and error-correcting codes requirements for NAND Flash memories.
Microelectron. Reliab., 2012

Ultra Low-Energy SRAM Design for Smart Ubiquitous Sensors.
IEEE Micro, 2012

A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, Ultra Low Leakage Power Memory Using Dynamic Cell Stability and a Dual Swing Data Link.
IEEE J. Solid State Circuits, 2012

A Fully Digital Delay Line Based GHz Range Multimode Transmitter Front-End in 65-nm CMOS.
IEEE J. Solid State Circuits, 2012

An 8-Bit, 40-Instructions-Per-Second Organic Microprocessor on Plastic Foil.
IEEE J. Solid State Circuits, 2012

Towards a Fast and Hardware Efficient Sub-MM Precision Ranging System.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

High Resolution Time-of-arrival for a Cm-precise Super 10 Meter 802.15.3C-based 60GHz OFDM Positioning Application.
Proceedings of the PECCS 2012, 2012

Design of a 150 mV Supply, 2 MIPS, 90nm CMOS, Ultra-Low-Power Microprocessor.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

Bidirectional communication in an HF hybrid organic/solution-processed metal-oxide RFID tag.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Bioelectronics for sustainable healthcare.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Picosecond pulse generation with nonlinear transmission lines in 90-nm CMOS for mm-wave imaging applications.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Design solutions for securing SRAM cell against power analysis.
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012

A 127 μW exact timing reference for Wireless Sensor Networks based on injection locking.
Proceedings of the 38th European Solid-State Circuit conference, 2012

Variation-resilient sub-threshold circuit solutions for ultra-low-power Digital Signal Processors with 10MHz clock frequency.
Proceedings of the 38th European Solid-State Circuit conference, 2012

Dual-output capacitive DC-DC converter with power distribution regulator in 90 nm CMOS.
Proceedings of the 38th European Solid-State Circuit conference, 2012

Design of a low-energy data processing architecture for WSN nodes.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Multiple Event Time-to-Digital Conversion-Based Pulse Digitization for a 250 MHz Pulse Radio Ranging Application.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Cross-cell interference variability aware model of fully planar NAND Flash memory including line edge roughness.
Microelectron. Reliab., 2011

A 4.4 pJ/Access 80 MHz, 128 kbit Variability Resilient SRAM With Multi-Sized Sense Amplifier Redundancy.
IEEE J. Solid State Circuits, 2011

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology.
IEEE J. Solid State Circuits, 2011

Unipolar Organic Transistor Circuits Made Robust by Dual-Gate Technology.
IEEE J. Solid State Circuits, 2011

An 8b organic microprocessor on plastic foil.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Circuits and systems engineering education through interdisciplinary team-based design projects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A low leakage 500MHz 2T embedded dynamic memory with integrated semi-transparent refresh.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

8T SRAM with Mimicked Negative Bit-lines and Charge Limited Sequential sense amplifier for wireless sensor nodes.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

Circuit design in organic semiconductor technologies.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

A 0.6V to 1.6V, 46μW voltage and temperature independent 48 MHz pulsed LC oscillator for RFID tags.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

A 190mV supply, 10MHz, 90nm CMOS, pipelined sub-threshold adder using variation-resilient circuit techniques.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

A low power time-of-arrival ranging front end based on a 8-channel 2.2mW, 53ps single-shot-precision Time-to-Digital converter.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

A/D Conversion Using Asynchronous Delta-Sigma Modulation and Time-to-Digital Conversion.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A Reconfigurable, 130 nm CMOS 108 pJ/pulse, Fully Integrated IR-UWB Receiver for Communication and Precise Ranging.
IEEE J. Solid State Circuits, 2010


Robust digital design in organic electronics by dual-gate technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 0.5 V-1.4 V supply-independent frequency-based analog-to-digital converter with fast start-up time for wireless sensor networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

All-digital differential VCO-based A/D conversion.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 4.4pJ/access 80MHz, 2K word } 64b memory with write masking feature and variability resilient multi-sized sense amplifier redundancy for wireless sensor nodes applications.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

An RDL-configurable 3D memory tier to replace on-chip SRAM.
Proceedings of the Design, Automation and Test in Europe, 2010

Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Performance Analysis of a Flexible Subsampling Receiver for Pulsed UWB Signals.
IEEE Trans. Wirel. Commun., 2009

A 3-tier UWB-based indoor localization system for ultra-low-power sensor networks.
IEEE Trans. Wirel. Commun., 2009

Design and Synthesis of Pareto Buffers Offering Large Range Runtime Energy/Delay Tradeoffs Via Combined Buffer Size and Supply Voltage Tuning.
IEEE Trans. Very Large Scale Integr. Syst., 2009

3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot.
Proc. IEEE, 2009

A 3.6 pJ/Access 480 MHz, 128 kb On-Chip SRAM With 850 MHz Boost Mode in 90 nm CMOS With Tunable Sense Amplifiers.
IEEE J. Solid State Circuits, 2009

A reconfigurable, 0.13µm CMOS 110pJ/pulse, fully integrated IR-UWB receiver for communication and sub-cm ranging.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 128b organic RFID transponder chip, including Manchester encoding and ALOHA anti-collision protocol, operating with a data rate of 1529b/s.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 0.4-1.4V 24MHz fully integrated 33µW, 104ppm/V supply-independent oscillator for RFIDs.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

RFID, where are they?
Proceedings of the 35th European Solid-State Circuits Conference, 2009

A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context.
Proceedings of the Design, Automation and Test in Europe, 2009

System-level power/performance evaluation of 3D stacked DRAMs for mobile applications.
Proceedings of the Design, Automation and Test in Europe, 2009

ActivaSC: a highly efficient and non-intrusive extension for activity-based analysis of SystemC models.
Proceedings of the 46th Design Automation Conference, 2009

3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV).
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
Synthesis of Runtime Switchable Pareto Buffers Offering Full Range Fine Grained Energy/Delay Trade-Offs.
J. Signal Process. Syst., 2008

Analysis of the QAC IR-UWB Receiver for Low Energy, Low Data-Rate Communication.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A Flexible, Ultra-Low-Energy 35 pJ/Pulse Digital Back-End for a QAC IR-UWB Receiver.
IEEE J. Solid State Circuits, 2008

UML for electronic systems design: a comprehensive overview.
Des. Autom. Embed. Syst., 2008

A low-power mixing DAC IR-UWB-receiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A/D conversion using an Asynchronous Delta-Sigma Modulator and a time-to-digital converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A Low Power, Reconfigurable IR-UWB System.
Proceedings of IEEE International Conference on Communications, 2008

A dual port dual width 90nm SRAM with guaranteed data retention at minimal standby supply voltage.
Proceedings of the ESSCIRC 2008, 2008

A 3.6pJ/access 480MHz, 128Kbit on-Chip SRAM with 850MHz boost mode in 90nm CMOS with tunable sense amplifiers to cope with variability.
Proceedings of the ESSCIRC 2008, 2008

A subsampling pulsed UWB demodulator based on a flexible complex SVD.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

2007
A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication.
IEEE J. Solid State Circuits, 2007

A Low-Power Embedded SRAM for Wireless Applications.
IEEE J. Solid State Circuits, 2007

<i>SmartMIMO</i>: An Energy-Aware Adaptive MIMO-OFDM Radio Link Control for Next-Generation Wireless Local Area Networks.
EURASIP J. Wirel. Commun. Netw., 2007

A 237mW aDSL2+ CO Line Driver in Standard 1.2V 0.13μ CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
Cross-layer power management in wireless networks and consequences on system-level architecture.
Signal Process., 2006

Reliability Issues in Deep Deep Submicron Technologies: Time-Dependent Variability and its Impact on Embedded System Design.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

SmartMIMO: Energy-Aware Adaptive MIMO-OFDM Radio Link Control for Wireless Local Area Networks.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

On the Combined Impact of Soft and Medium Gate Oxide Breakdown and Process Variability on the Parametric Figures of SRAM components.
Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006

Statistically Aware SRAM Memory Array Design.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

A High speed, Low Voltage to High Voltage Level Shifter in Standard 1.2V 0.13μm CMOS.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

UML for ESL design: basic principles, tools, and applications.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A Flexible Low Power Subsampling UWB Receiver Based on Line Spectrum Estimation Methods.
Proceedings of IEEE International Conference on Communications, 2006

From UML/SysML to Matlab/Simulink: current state and future perspectives.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Energy Efficient Memory Architecture for High Speed Decoding of Block Turbo-Codes with the Fang-Buda Algorithm.
J. VLSI Signal Process., 2005

Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs.
IEEE Trans. Very Large Scale Integr. Syst., 2005

System design of an ultra-low power, low data rate, pulsed UWB receiver in the 0-960 MHz band.
Proceedings of IEEE International Conference on Communications, 2005

The SysML profile for embedded system modelling.
Proceedings of the Forum on specification and Design Languages, 2005

Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules.
Proceedings of the 2005 Design, 2005

UML 2 and SysML: An Approach to Deal with Complexity in SoC/NoC Design.
Proceedings of the 2005 Design, 2005

Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?
Proceedings of the 2005 Design, 2005

Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives.
Proceedings of the 2005 Design, 2005

2004
Architectures for low power ultra-wideband radio receivers in the 3.1-5GHz band for data rates < 10Mbps.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

2003
A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for System on Chip Verification.
Proceedings of the 2003 Design, 2003


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