Nirmal Kumar Boran

Orcid: 0000-0003-3942-7899

According to our database1, Nirmal Kumar Boran authored at least 9 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2024
MIST: Many-ISA Scheduling Technique for Heterogeneous-ISA Architectures.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

GNNDLD: Graph Neural Network with Directional Label Distribution.
Proceedings of the 16th International Conference on Agents and Artificial Intelligence, 2024

2023
Secure KNN Computation on Cloud.
Proceedings of the Information Systems Security - 19th International Conference, 2023

2022
PASS-P: Performance and Security Sensitive Dynamic Cache Partitioning.
Proceedings of the 19th International Conference on Security and Cryptography, 2022

2021
Fine-Grained Scheduling in Heterogeneous-ISA Architectures.
IEEE Comput. Archit. Lett., 2021

On Disabling Prefetcher to Amplify Cache Side Channels.
Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

2020
Classification based scheduling in Heterogeneous ISA Architectures.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

2019
Performance Modelling and Dynamic Scheduling on Heterogeneous-ISA Multi-core Architectures.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

2016
Performance modelling of heterogeneous ISA multicore architectures.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016


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