Nobuhiro Tomabechi

According to our database, Nobuhiro Tomabechi authored at least 16 papers between 1986 and 2009.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2009

Traveling-salesman game with multiple competitors/cooperators and simultaneous move search algorithm.

Nobuhiro Tomabechi, Yoshichika Fujioka

Proceedings of the 2009 International IEEE Consumer Electronics Society's Games Innovations Conference, 2009

2005

VLSI architecture based on packet data transfer scheme and its application.

Yuya Homma, Michitaka Kameyama, Yoshichika Fujioka, Nobuhiro Tomabechi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2002

Design of a high-speed RSA encryption processor based on the residue table for redundant binary numbers.

Nobuhiro Tomabechi, Teruki Ito

Syst. Comput. Jpn., 2002

2001

Defect-tolerance design of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers.

Nobuhiro Tomabechi, Teruki Ito

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000

Design of a WSI scale parallel processor for intelligent robot control based on a dynamic reconfiguration of multi-operand arithmetic units.

Yoshichika Fujioka, Nobuhiro Tomabechi

Syst. Comput. Jpn., 2000

Design of a high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers.

Nobuhiro Tomabechi, Teruki Ito

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

Multi-Dimensional Subsystem-Dividing for Yield Enhancement in Defect-Tolerant WSI Systems.

Nobuhiro Tomabechi

Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

1998

Redundancy design of a wafer scale two-dimensional FFT processor.

Shyouji Kanazawa, Nobuhiro Tomabechi

Syst. Comput. Jpn., 1998

1997

Redundancy design of a wafer scale and high-speed FFT processor.

Nobuhiro Tomabechi, Shyouji Kanazawa

Syst. Comput. Jpn., 1997

CAI oriented algorithm for Boolean-function minimization based on the ternaryKarnaugh map.

Nobuhiro Tomabechi

Syst. Comput. Jpn., 1997

The effect of hardware needed for redundant interconnection lines and exchangingswitches on the yield of VLSI chips with redundan.

Nobuhiro Tomabechi

Syst. Comput. Jpn., 1997

1996

WSI oriented design for highly reliable systems based on the residue number system.

Nobuhiro Tomabechi

Syst. Comput. Jpn., 1996

Design of a Parallel Processor for Visual Feedback Control Based on the Reconfiguration of Word Length.

Yoshichika Fujioka, Nobuhiro Tomabechi

J. Robotics Mechatronics, 1996

1991

A defect recovery method for ulsi/ wsi arithmetic operation systems based on residue number systems.

Nobuhiro Tomabechi

Syst. Comput. Jpn., 1991

1989

Counter-based residue arithmetic circuit for easily testable VLSI digital signal processing systems.

Nobuhiro Tomabechi

Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

1986

Design of lsi-oriented digital signal processing system Based on Pulse-Train Residue Arithmetic Circuits.

Nobuhiro Tomabechi, Michitaka Kameyama, Tatsuo Higuchi

Syst. Comput. Jpn., 1986