Nobutaka Kito

According to our database, Nobutaka Kito authored at least 9 papers between 2008 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Concurrent Error Detectable Carry Select Adder with Easy Testability.

Nobutaka Kito, Naofumi Takagi

IEEE Trans. Computers, 2019

Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses.

Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi

IPSJ Trans. Syst. LSI Des. Methodol., 2019

Rapid Single-Flux-Quantum Truncated Multiplier Based on Bit-Level Processing.

Nobutaka Kito, Ryota Odaka, Kazuyoshi Takagi

IEICE Trans. Electron., 2019

2017

Floating-Point Multiplier with Concurrent Error Detection Capability by Partial Duplication.

Nobutaka Kito, Kazushi Akimoto, Naofumi Takagi

IEICE Trans. Inf. Syst., 2017

2014

Circuit Description and Design Flow of Superconducting SFQ Logic Circuits.

Kazuyoshi Takagi, Nobutaka Kito, Naofumi Takagi

IEICE Trans. Electron., 2014

2013

Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication.

Nobutaka Kito, Naofumi Takagi

IEICE Trans. Inf. Syst., 2013

2012

A C-Testable Multiple-Block Carry Select Adder.

Nobutaka Kito, Shinichi Fujii, Naofumi Takagi

IEICE Trans. Inf. Syst., 2012

2010

A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier.

Nobutaka Kito, Kensuke Hanai, Naofumi Takagi

IEICE Trans. Inf. Syst., 2010

2008

Level-Testability of Multi-operand Adders.

Nobutaka Kito, Naofumi Takagi

Proceedings of the 17th IEEE Asian Test Symposium, 2008