Kazuyoshi Takagi

According to our database, Kazuyoshi Takagi authored at least 39 papers between 1998 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Splitter-Aware Multiterminal Routing With Length-Matching Constraint for RSFQ Circuits.

Mingyang Kou, Pei-Yi Cheng, Jun Zeng, Tsung-Yi Ho, Kazuyoshi Takagi, Hailong Yao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

2020

mROS: A Lightweight Runtime Environment of ROS 1 nodes for Embedded Devices.

Hideki Takase, Tomoya Mori, Kazuyoshi Takagi, Naofumi Takagi

J. Inf. Process., 2020

2019

Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses.

Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi

IPSJ Trans. Syst. LSI Des. Methodol., 2019

Rapid Single-Flux-Quantum Truncated Multiplier Based on Bit-Level Processing.

Nobutaka Kito, Ryota Odaka, Kazuyoshi Takagi

IEICE Trans. Electron., 2019

mROS: A Lightweight Runtime Environment for Robot Software Components onto Embedded Devices.

Hideki Takase, Tomoya Mori, Kazuyoshi Takagi, Naofumi Takagi

Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2019

2018

Algorithms for Evaluating the Matrix Polynomial <i>I</i>+<i>A</i>+<i>A</i>²+...+<i>A</i>^<i>N</i>-1 with Reduced Number of Matrix Multiplications.

Kotaro Matsumoto, Kazuyoshi Takagi, Naofumi Takagi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Multi-terminal routing with length-matching for rapid single flux quantum circuits.

Pei-Yi Cheng, Kazuyoshi Takagi, Tsung-Yi Ho

Proceedings of the International Conference on Computer-Aided Design, 2018

Design concept of a lightweight runtime environment for robot software components onto embedded devices: work-in-progress.

Hideki Takase, Tomoya Mori, Kazuyoshi Takagi, Naofumi Takagi

Proceedings of the International Conference on Embedded Software, 2018

2016

RSFQ 4-bit Bit-Slice Integer Multiplier.

Guang-Ming Tang, Kazuyoshi Takagi, Naofumi Takagi

IEICE Trans. Electron., 2016

High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation.

Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi

IEICE Trans. Electron., 2016

An evaluation framework of OS-level power managements for the big.LITTLE architecture.

Hideki Takase, Kazumi Aono, Yutaka Matsubara, Kazuyoshi Takagi, Naofumi Takagi

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

2015

An Allocation Optimization Method for Partially-reliable Scratch-pad Memory in Embedded Systems.

Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi

IPSJ Trans. Syst. LSI Des. Methodol., 2015

A Verification Method for Single-Flux-Quantum Circuits Using Delay-Based Time Frame Model.

Takahiro Kawaguchi, Kazuyoshi Takagi, Naofumi Takagi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

2014

Circuit Description and Design Flow of Superconducting SFQ Logic Circuits.

Kazuyoshi Takagi, Nobutaka Kito, Naofumi Takagi

IEICE Trans. Electron., 2014

Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis.

Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm² Nb Process.

Xizhu Peng, Yuki Yamanashi, Nobuyuki Yoshikawa, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi, Mutsuo Hidaka

IEICE Trans. Electron., 2014

Nb 9-Layer Fabrication Process for Superconducting Large-Scale SFQ Circuits and Its Process Evaluation.

Shuichi Nagasawa, Kenji Hinode, Tetsuro Satoh, Mutsuo Hidaka, Hiroyuki Akaike, Akira Fujimaki, Nobuyuki Yoshikawa, Kazuyoshi Takagi, Naofumi Takagi

IEICE Trans. Electron., 2014

Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors.

Akira Fujimaki, Masamitsu Tanaka, Ryo Kasagi, Katsumi Takagi, Masakazu Okada, Yuhi Hayakawa, Kensuke Takata, Hiroyuki Akaike, Nobuyuki Yoshikawa, Shuichi Nagasawa, Kazuyoshi Takagi, Naofumi Takagi

IEICE Trans. Electron., 2014

An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Maximize the Operation Quality.

Kazumi Aono, Atsushi Iwata, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi

Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

2013

A Buffering Method for Parallelized Loop with Non-Uniform Dependencies in High-Level Synthesis.

Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi

Proceedings of the Algorithms and Architectures for Parallel Processing, 2013

2012

Fast inversion algorithm in GF(2^m) suitable for implementation with a polynomial multiply instruction on GF(2).

Katsuki Kobayashi, Naofumi Takagi, Kazuyoshi Takagi

IET Comput. Digit. Tech., 2012

A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition.

Kazuhiro Nakamura, Ryo Shimazaki, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi

IEICE Trans. Electron., 2012

2011

Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits.

Kazuyoshi Takagi, Yuki Ito, Shota Takeshima, Masamitsu Tanaka, Naofumi Takagi

IEICE Trans. Electron., 2011

2010

Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on A* Algorithm.

Masamitsu Tanaka, Koji Obata, Yuki Ito, Shota Takeshima, Motoki Sato, Kazuyoshi Takagi, Naofumi Takagi, Hiroyuki Akaike, Akira Fujimaki

IEICE Trans. Electron., 2010

A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing.

Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi

IEICE Trans. Inf. Syst., 2010

2008

A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits.

Koji Obata, Kazuyoshi Takagi, Naofumi Takagi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems.

Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital Circuits.

Koji Obata, Kazuyoshi Takagi, Naofumi Takagi

IEICE Trans. Electron., 2007

Logic Synthesis Method for Dual-Rail RSFQ Digital Circuits Using Root-Shared Binary Decision Diagrams.

Koji Obata, Kazuyoshi Takagi, Naofumi Takagi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

VLSI CAD Education and Exercise Course with Public Domain Tools.

Satoshi Komatsu, Kazuyoshi Takagi, Masahiro Fujita, Kunihiro Asada

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

An Algorithm for Inversion in GF(2^m) Suitable for Implementation Using a Polynomial Multiply Instruction on GF(2).

Katsuki Kobayashi, Naofumi Takagi, Kazuyoshi Takagi

Proceedings of the 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 2007

2006

A Hardware Algorithm for Integer Division Using the SD2 Representation.

Naofumi Takagi, Shunsuke Kadowaki, Kazuyoshi Takagi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

A transduction-based framework to synthesize RSFQ circuits.

Shigeru Yamashita, Katsunori Tanaka, Hideyuki Takada, Koji Obata, Kazuyoshi Takagi

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

A Hardware Algorithm for Integer Division.

Naofumi Takagi, Shunsuke Kadowaki, Kazuyoshi Takagi

Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2003

Digit-Recurrence Algorithm for Computing Reciprocal Square-Root.

Naofumi Takagi, Daisuke Matsuoka, Kazuyoshi Takagi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

2002

A VLSI Algorithm for Division in GF(2^m) Based on Extended Binary GCD Algorithm.

Yasuaki Watanabe, Naofumi Takagi, Kazuyoshi Takagi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

2001

A Fast Algorithm for Multiplicative Inversion in GF(2m) Using Normal Basis.

Naofumi Takagi, Jun-ichi Yoshiki, Kazuyoshi Takagi

IEEE Trans. Computers, 2001

2000

An application specific Java processor with reconfigurabilities.

Shinji Kimura, Hiroyuki Kida, Kazuyoshi Takagi, Tatsumori Abematsu, Katsumasa Watanabe

Proceedings of ASP-DAC 2000, 2000

1998

Waiting false path analysis of sequential logic circuits for performance optimization.

Kazuhiro Nakamura, Kazuyoshi Takagi, Shinji Kimura, Katsumasa Watanabe

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998