Noriyuki Tanino

According to our database, Noriyuki Tanino authored at least 2 papers between 1990 and 1999.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1999

A 12-ps-resolution digital variable-delay macro cell on GaAs 100 K-gates gate array using a meshed air bridge structure.

Akira Ohta, Norio Higashisaka, Tetsuya Heima, Takayuki Hisaka, Hirofumi Nakano, Ryuji Ohmura, Tadashi Takagi, Noriyuki Tanino

IEEE J. Solid State Circuits, 1999

1990

A 7-ns/850-mW GaAs 4-kb SRAM with little dependence on temperature.

Hiroshi Makino, Shuichi Matsue, Minoru Noda, Noriyuki Tanino, Satoshi Takano, Kazuo Nishitani, Shimpei Kayano

IEEE J. Solid State Circuits, October, 1990