Olivier Serres

According to our database1, Olivier Serres authored at least 23 papers between 2007 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2021
Configurable Network Protocol Accelerator (COPA).
IEEE Micro, 2021

2020
COnfigurable Network Protocol Accelerator (COPA) <sup>†</sup> : An Integrated Networking/Accelerator Hardware/Software Framework.
Proceedings of the IEEE Symposium on High-Performance Interconnects, 2020

2017
HPC-Oriented Toolchain for Hardware Simulators.
Proceedings of the 2017 IEEE International Conference on Cluster Computing, 2017

2016
Enabling PGAS Productivity with Hardware Support for Shared Address Mapping: A UPC Case Study.
ACM Trans. Archit. Code Optim., 2016

Exploiting Hierarchical Locality in Deep Parallel Architectures.
ACM Trans. Archit. Code Optim., 2016

PGAS Access Overhead Characterization in Chapel.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

2015
Adaptive Cache Coherence Mechanisms with Producer-Consumer Sharing Optimization for Chip Multiprocessors.
IEEE Trans. Computers, 2015

Energy Efficient Job Co-scheduling for High-Performance Parallel Computing Clusters.
Proceedings of the 2015 IEEE International Conference on Smart City/SocialCom/SustainCom/DataCom/SC2 2015, 2015

Big Data Techniques for Scalable In-Band and Out-of-Band HPC Energy Measurement.
Proceedings of the 2015 IEEE International Conference on Smart City/SocialCom/SustainCom/DataCom/SC2 2015, 2015

2014
Bandwidth Adaptive Cache Coherence Optimizations for Chip Multiprocessors.
Int. J. Parallel Program., 2014

Where should the threads go? Leveraging hierarchical data locality to solve the thread affinity dilemma.
Proceedings of the 20th IEEE International Conference on Parallel and Distributed Systems, 2014

Leveraging Hierarchical Data Locality in Parallel Programming Models.
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

Hardware support for address mapping in PGAS languages: a UPC case study.
Proceedings of the Computing Frontiers Conference, CF'14, 2014

2013
Performance Pattern of Unified Parallel C on Multi-core Clusters.
Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing, 2013

2012
Bandwidth Adaptive Write-update Optimizations for Chip Multiprocessors.
Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012

2011
An Architecture for Reconfigurable Multi-core Explorations.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Address Translation Optimization for Unified Parallel C Multi-dimensional Arrays.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Reflex Barrier: A Scalable Network-Based Synchronization Barrier.
Proceedings of the 17th IEEE International Conference on Parallel and Distributed Systems, 2011

2010
Reconfiguration and Communication-Aware Task Scheduling for High-Performance Reconfigurable Computing.
ACM Trans. Reconfigurable Technol. Syst., 2010

Parameterized Hardware Design on Reconfigurable Computers: An Image Processing Case Study.
Int. J. Reconfigurable Comput., 2010

Efficient cache design for solid-state drives.
Proceedings of the 7th Conference on Computing Frontiers, 2010

2009
RDMS: A hardware task scheduling algorithm for Reconfigurable Computing.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

2007
An Efficient and Scalable Management of Ontology.
Proceedings of the Advances in Databases: Concepts, 2007


  Loading...