Vikram K. Narayana

Orcid: 0000-0002-3878-0634

According to our database1, Vikram K. Narayana authored at least 30 papers between 2009 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2020
ROC: A Reconfigurable Optical Computer for Simulating Physical Processes.
ACM Trans. Parallel Comput., 2020

2018
Corrigendum: Software for Brain Network Simulations: A Comparative Study.
Frontiers Neuroinformatics, 2018

D<sup>3</sup>NoC: a dynamic data-driven hybrid photonic plasmonic NoC.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

2017
MorphoNoC: Exploring the design space of a configurable hybrid NoC using nanophotonics.
Microprocess. Microsystems, 2017

Software for Brain Network Simulations: A Comparative Study.
Frontiers Neuroinformatics, 2017

Integrated Nanophotonics Architecture for Residue Number System Arithmetic.
CoRR, 2017

D3NOC: Dynamic Data-Driven Network On Chip in Photonic Electronic Hybrids.
CoRR, 2017

Optimizing thin client caches for mobile cloud computing: : Design space exploration using genetic algorithms.
Concurr. Comput. Pract. Exp., 2017

HyPPI NoC: Bringing Hybrid Plasmonics to an Opto-Electronic Network-on-Chip.
Proceedings of the 46th International Conference on Parallel Processing, 2017

2016
A Universal Multi-Hierarchy Figure-of-Merit for On-Chip Computing and Communications.
CoRR, 2016

Moore's Law in CLEAR Light.
CoRR, 2016

2015
Reordering GPU Kernel Launches to Enable Efficient Concurrent Execution.
CoRR, 2015

Efficient Resource Sharing Through GPU Virtualization on Accelerated High Performance Computing Systems.
CoRR, 2015

A Power-Aware Symbiotic Scheduling Algorithm for Concurrent GPU Kernels.
Proceedings of the 21st IEEE International Conference on Parallel and Distributed Systems, 2015

2014
Methodology for adapting on-chip interconnect architectures.
IET Comput. Digit. Tech., 2014

"CERE": A CachE Recommendation Engine: Efficient Evolutionary Cache Hierarchy Design Space Exploration.
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

Symbiotic scheduling of concurrent GPU kernels for performance and energy optimizations.
Proceedings of the Computing Frontiers Conference, CF'14, 2014

2013
Exploring Graphics Processing Unit (GPU) Resource Sharing Efficiency for High Performance Computing.
Comput., 2013

2012
Efficient Mapping of Task Graphs onto Reconfigurable Hardware Using Architectural Variants.
IEEE Trans. Computers, 2012

A scalability study of interconnect architectures for System-on-Chip.
Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012

Accelerated high-performance computing through efficient multi-process GPU resource sharing.
Proceedings of the Computing Frontiers Conference, CF'12, 2012

Distributed Shared Memory Programming in the Cloud.
Proceedings of the 12th IEEE/ACM International Symposium on Cluster, 2012

2011
An Architecture for Reconfigurable Multi-core Explorations.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

GPU Resource Sharing and Virtualization on High Performance Computing Systems.
Proceedings of the International Conference on Parallel Processing, 2011

A Static Task Scheduling Framework for Independent Tasks Accelerated Using a Shared Graphics Processing Unit.
Proceedings of the 17th IEEE International Conference on Parallel and Distributed Systems, 2011

Scaling scientific applications on clusters of hybrid multicore/GPU nodes.
Proceedings of the 8th Conference on Computing Frontiers, 2011

2010
Reconfiguration and Communication-Aware Task Scheduling for High-Performance Reconfigurable Computing.
ACM Trans. Reconfigurable Technol. Syst., 2010

Efficient cache design for solid-state drives.
Proceedings of the 7th Conference on Computing Frontiers, 2010

Space and Time Sharing of Reconfigurable Hardware for Accelerated Parallel Processing.
Proceedings of the Reconfigurable Computing: Architectures, 2010

2009
Efficient Mapping of Hardware Tasks on Reconfigurable Computers Using Libraries of Architecture Variants.
Proceedings of the FCCM 2009, 2009


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