Omar Abdelfattah

According to our database, Omar Abdelfattah authored at least 10 papers between 2010 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

A Top-Down Design Methodology Encompassing Components Variations Due to Wide-Range Operation in Frequency Synthesizer PLLs.

Omar Abdelfattah, George Gal, Gordon W. Roberts, Ishiang Shih, Yi-Chi Shih

IEEE Trans. Very Large Scale Integr. Syst., 2016

2015

An Ultra-Low-Voltage CMOS Process-Insensitive Self-Biased OTA With Rail-to-Rail Input Range.

Omar Abdelfattah, Gordon W. Roberts, Ishiang Shih, Yi-Chi Shih

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 0.6V-supply bandgap reference in 65 nm CMOS.

Omar Abdelfattah, Ishiang Shih, Gordon W. Roberts, Yi-Chi Shih

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

A 0.55-V 1-GHz frequency synthesizer PLL for ultra-low-voltage ultra-low-power applications.

Omar Abdelfattah, Ishiang Shih, Gordon W. Roberts, Yi-Chi Shih

Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

A 0.35-V bulk-driven self-biased OTA with rail-to-rail input range in 65 nm CMOS.

Omar Abdelfattah, Gordon W. Roberts, Ishiang Shih, Yi-Chi Shih

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

Optimization of LC-VCO tuning range under different inductor/varactor losses limitations.

Omar Abdelfattah, Ishiang Shih, Gordon W. Roberts, Yi-Chi Shih

Proceedings of the IEEE 27th Canadian Conference on Electrical and Computer Engineering, 2014

2013

Analytical comparison between passive loop filter topologies for frequency synthesizer PLLs.

Omar Abdelfattah, Ishiang Shih, Gordon W. Roberts

Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

A simple analog CMOS design tool using transistor dimension-independent parameters.

Omar Abdelfattah, Ishiang Shih, Gordon W. Roberts

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012

A 30-40 GHz fractional-N frequency synthesizer development using a Verilog-A high-level design methodology.

George Gal, Omar Abdelfattah, Gordon W. Roberts

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

2010

Direct residue-to-analog conversion scheme based on Chinese Remainder Theorem.

Omar Abdelfattah, Andraws I. Swidan, Zeljko Zilic

Proceedings of the 17th IEEE International Conference on Electronics, 2010