Gordon W. Roberts

According to our database1, Gordon W. Roberts authored at least 127 papers between 1993 and 2020.

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Bibliography

2020
Using Optimized Butterworth-Based ΣΔ Bitstreams for the Testing of High-Resolution Data Converters.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

The Impact of the Scaled-Down CMOS Technologies on the Step Response Degradation Caused by the Pole-Zero Doublets in the OTAs.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

2019
A Second-Order Bandpass $\Delta\Sigma$ Time-to-Digital Converter With Negative Time-Mode Feedback.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Opportunities and Challenges in Desktop-Inkjet Based Flexible Hybrid Electronics.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Selecting the Fastest Settling-Time Filter in PDM-based DACs used for Dynamic Calibration Applications.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Investigating the Developments on the Frequency Compensation Techniques of the Two-Stage OTAs - A Brief Guide and Updated Review -.
Proceedings of the 31st International Conference on Microelectronics, 2019

On the Design of DACs for Dynamic Calibration Applications using Periodic Sequences from ΣΔ Modulators.
Proceedings of the 2019 IEEE Canadian Conference of Electrical and Computer Engineering, 2019

2018
Cascade and LC Ladder-Based Filter Realizations Using Synchronous Time-Mode Signal Processing.
IEEE Trans. Very Large Scale Integr. Syst., 2018

The Peak-SNR Performances of Voltage-Mode versus Time-Mode Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Design of High-Order Type-II Delay-Locked Loops With a Fast-Settling-Zero-Overshoot Step Response and Large Jitter-Rejection Capabilities.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A coherent subsampling test system arrangement suitable for phase domain measurements.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

An All-Digital High-Resolution Programmable Time-Difference Amplifier Based on Time Latch.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
All-Digital Time-Mode Direct-Form All-Pole Biquadratic Filter Realization.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A time-mode LDI-based resonator for a band-pass ΔΣ TDC.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Passive sensors for flexible hybrid-printed electronics' systems: An IC designer view.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

The analytic expression of the output spectrum of ΔΣ ADCs with nonlinear binary-weighted DACs and Gaussian input signals.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
A Top-Down Design Methodology Encompassing Components Variations Due to Wide-Range Operation in Frequency Synthesizer PLLs.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Synthesis of High Gain Operational Transconductance Amplifiers for Closed-Loop Operation Using a Generalized Controller-Based Compensation Method.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A Jitter Injection Signal Generation and Extraction System for Embedded Test of High-Speed Data I/O.
J. Electron. Test., 2016

A digitally programmable 50-150dB DC gain operational transconductance amplifier in 130nm CMOS.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Top-down design and synthesis of inherently-stable integrator-based high-order amplifiers.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Experimental operation of time-mode building blocks using a time-mode switched-delay unit.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Mixed-signal ATE technology and its impact on today's electronic system.
Proceedings of the 2016 IEEE International Test Conference, 2016

Design of high-order type-II delay-locked loops using a Gaussian transfer function approach.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Low-cost trimmable manufacturing methods for printable electronics.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
An Ultra-Low-Voltage CMOS Process-Insensitive Self-Biased OTA With Rail-to-Rail Input Range.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Guest Editors' Introduction: Speeding Up Analog Integration and Test for Mixed-Signal SoCs.
IEEE Des. Test, 2015

A 0.6V-supply bandgap reference in 65 nm CMOS.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Wide linear range voltage-controlled delay unit for time-mode signal processing.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

An embedded probabilistic extraction unit for on-chip jitter measurements.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 0.35-V bulk-driven self-biased OTA with rail-to-rail input range in 65 nm CMOS.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Quick and easy CMOS amplifier design and optimization.
Proceedings of the European Conference on Circuit Theory and Design, 2015

2014
Reducing the analog-digital productivity gap using time-mode signal processing.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

All-digital Time-Mode elliptic filters based on the operational simulation of LC ladders.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Towards a general purpose mixed-signal instrumentation layer in the die stack of a 3D-SIC.
Proceedings of the 19th IEEE European Test Symposium, 2014

Testability and reliability enhancement techniques.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

Sub-gate-delay edge-control of a clock signal using DLLs and ΣΔ modulation techniques.
Proceedings of the IEEE 27th Canadian Conference on Electrical and Computer Engineering, 2014

Optimization of LC-VCO tuning range under different inductor/varactor losses limitations.
Proceedings of the IEEE 27th Canadian Conference on Electrical and Computer Engineering, 2014

2013
Special session 12B: Panel post-silicon validation & test in huge variance era.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Welcome message.
Proceedings of the 2013 IEEE International Test Conference, 2013

A simple analog CMOS design tool using transistor dimension-independent parameters.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Anti-Imaging Time-Mode Filter Design Using a PLL Structure With Transfer Function DFT.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A Digital Implementation of a Dual-Path Time-to-Time Integrator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

High Speed On-Chip Signal Generation for Debug and Diagnosis.
J. Electron. Test., 2012

A 30-40 GHz fractional-N frequency synthesizer development using a Verilog-A high-level design methodology.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Track and hold for Giga-sample ADC applications using CMOS technology.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A probabilistic test instrument using a ΣΔ-encoded amplitude/phase-signal generation technique.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Time-mode reconstruction iir filters for ΣΔ phase modulation applications.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Programmable phase/frequency generator for system debug and diagnosis using the IEEE 1149.1 test bus.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
A Brief Introduction to Time-to-Digital and Digital-to-Time Converters.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

A low-cost ATE phase signal generation technique for test applications.
Proceedings of the 2011 IEEE International Test Conference, 2010

Jitter generation and capture using phase-domain sigma-delta encoding.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
Delta-Sigma A/D Conversion Via Time-Mode Signal Processing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Mixed-Signal Production Test: A Measurement Principle Perspective.
IEEE Des. Test Comput., 2009

Optimizing CMOS Amplifier Design Directly in SPICE without the Need for Additional Mathematical Models.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Sampled-data IIR Filtering using Time-mode Signal Processing Circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A Semi-digital Interface for Capacitive Sensors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Test methods and ICs for high-speed serdes.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Embedded Measurement of GHz Digital Signals With Time Amplification in CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Time-domain analog signal processing techniques.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Test Methods For Sigma-Delta Data Converters and Related Devices.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Generating Test Signals for Noise-Based NPR/ACPR Type Tests in Production.
Proceedings of the 2008 IEEE International Test Conference, 2008

A metastability-independent time-to-voltage converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Session 4 - High-speed test, characterization, and debug.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
70-GHz Effective Sampling Time-Base On-Chip Oscilloscope in CMOS.
IEEE J. Solid State Circuits, 2007

Delta-Sigma Analog-to-Digital Conversion via Time-Mode Signal Processing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Low-Voltage Analog Switch in Deep Submicron CMOS: Design Technique and Experimental Measurements.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

A Predictable Robust Fully Programmable Analog Gaussian Noise Source for Mixed-Signal/Digital ATE.
Proceedings of the 2006 IEEE International Test Conference, 2006

Process-insensitive modulated-clock voltage comparator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A CMOS circuit for embedded GHz measurement of digital signal rise time degradation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 70-GHz Effective Sampling Rate On-Chip Oscilloscope with Time-Domain Digitization.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
Reducing Measurement Uncertainty in a DSP-Based Mixed-Signal Test Environment Without Increasing Test Time.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Low power delta-sigma Modulator for ADSL applications in a low-Voltage CMOS technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

A Distributed Synchronized Clocking Method.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Low-voltage CMOS analog bootstrapped switch for sample-and-hold circuit: design and chip characterization.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Noise and reliability containment approaches.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
A jitter characterization system using a component-invariant Vernier delay line.
IEEE Trans. Very Large Scale Integr. Syst., 2004

A High-Resolution Flash Time-to-Digital Converter and Calibration Scheme.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

A High-Throughput 5 GBps Timing and Jitter Test Module Featuring Localized Processing.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

A CMOS time amplifier for Femto-second resolution timing measurement.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A calibration technique for a high-resolution flash time-to-digital converter.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Techniques for high-frequency integrated test and measurement.
IEEE Trans. Instrum. Meas., 2003

ITC Highlights.
IEEE Des. Test Comput., 2003

ITC 2003: Breaking Test Interface Bottlenecks.
IEEE Des. Test Comput., 2003

A DC current measurement circuit for on-chip applications.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
Mixed-Signal BIST: Fact or Fiction.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Test and Evaluation of Multiple Embedded Mixed-Signal Test Cores.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

A 10-bit 1 MS/s 3-step ADC with bitstream-based sub-DAC and sub-ADC calibration.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Temperature compensated CMOS voltage reference.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Analog and Mixed Signal Benchmark Circuit Development: Who Needs Them?
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

A robust DC current generation and measurement technique for deep submicron circuits.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A design strategy for a 1-V rail-to-rail input/output CMOS opamp.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A 1-V, 10-bit rail-to-rail successive approximation analog-to-digital converter in standard 0.18 um CMOS technology.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

The development of bipolar log domain filters in a standard CMOS process.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Top-down analog design methodology using Matlab and Simulink.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A CMOS digitally programmable current steering semidigital FIR reconstruction filter.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Strategies for on-chip sub-nanosecond signal capture and timing measurements.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Increasing the performance of arbitrary waveform generators using periodic sigma-delta modulated streams.
IEEE Trans. Instrum. Meas., 2000

A stand-alone integrated test core for time and frequency domain measurements.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Low power/low voltage high speed CMOS differential track and latch comparator with rail-to-rail input.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
Making complex mixed-signal telecommunication integrated circuits testable.
IEEE Commun. Mag., 1999

A 1.2 V NPN-only log-domain integrator.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
An integration of memory-based analog signal generation into current DFT architectures.
IEEE Trans. Instrum. Meas., 1998

Stimulus generation for built-in self-test of charge-pump phase-locked loops.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

A high speed and area efficient on-chip analog waveform extractor.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Increasing the performance of arbitrary waveform generators using sigma-delta coding techniques.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997
Delta-sigma oscillators: versatile building blocks.
Int. J. Circuit Theory Appl., 1997

On-Chip Measurement of the Jitter Transfer Function of Charge-Pump Phase-Locked Loops.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Signal Generation Using Periodic Single-and Multi-Bit Sigma-Delta Modulated Streams.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1996
Metrics, techniques and recent developments in mixed-signal testing.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995
A Bulti-in Self-Test Strategy for Wireless Communication Systems.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Re-examining the Needs of the Mixed-Signal Test.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Arbitrary-Precision Signal Generation for Bandlimited Mixed-Signal Testing.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Bandpass Signal Generation Using Delta-Sigma Modulation Techniques.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Calculating Distortion Levels in Sampled-Data Circuits Using SPICE.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Log-Domain Filters Based on LC Ladder Synthesis.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
A BIST technique for a frequency response and intermodulation distortion test of a sigma-delta ADC.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

An Analog Multi-Tone Signal Generator for Built-In Self-Test Applications.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

A Comparison of First and Second Generation Switched-Current Cells.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

VAMP: A Hierarchical Framework for Design for Manufacturability.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
A BIST Scheme for an SNR Test of a Sigma-Delta ADC.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Towards Built-In-Self-Test for SNR Testing of a Mixed-Signal IC.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

A 5th Order Bilinear Switched-current Chebyshev Filter.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

A High-Quality Analog Oscillator Using Oversampling D/A Conversion Techniques.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Designing Operational Transconductance Amplifiers for Low Voltage Operation.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Predicting Harmonic Distortion in Switched-current Memory Circuits.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993


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