Gordon W. Roberts
Orcid: 0000-0002-4880-0272Affiliations:
- McGill University, Montreal, Canada
According to our database1,
Gordon W. Roberts
authored at least 155 papers
between 1993 and 2024.
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Bibliography
2024
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
2023
An In-Circuit Test Method for Measuring the Bonding Resistances of Individual IC Pins From an Interconnected Multiple IC Assembly of Flexible Hybrid Electronics.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
Scalable Multi-Stage CMOS OTAs With a Wide C<sub>L</sub>-Drivability Range Using Low-Frequency Zeros.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023
An Area Efficient and Inductorless Implementation of Continuous-Time Linear Equalization Scheme for High Speed and Low Noise TIA Designs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
Identifying A(s) and β(s) in Single-Loop Feedback Circuits Using the Intermediate Transfer Function Approach.
Sensors, 2022
A 83-GHz and 68-dBΩ TIA with 2.3 pA/√ Hz: Towards High Speed and Low Noise Optical Receivers.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022
2021
An Area-Efficient High-Resolution Segmented ΣΔ-DAC for Built-In Self-Test Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Generalized Relationship Between Frequency Response and Settling Time of CMOS OTAs: Toward Many-Stage Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Extracting RLC Parasitics From a Flexible Electronic Hybrid Assembly Using On-Chip ESD Protection Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A Modified Nyquist Stability Criteria that Takes into Account Input/Output Circuit Loading Effects.
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021
Single-Loop Feedback Parameter Extraction Method for Stability Analysis of Electronic Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
Optimized Periodic ΣΔ Bitstreams for DC Signal Generation Used in Dynamic Calibration Applications.
IEEE Open J. Circuits Syst., 2020
Using Optimized Butterworth-Based ΣΔ Bitstreams for the Testing of High-Resolution Data Converters.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
The Impact of the Scaled-Down CMOS Technologies on the Step Response Degradation Caused by the Pole-Zero Doublets in the OTAs.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020
An In-Situ Technique for Measuring the Individual Contact Resistance between the Pins of an IC Package and the Board of a Flexible Hybrid Electronic System.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
A Second-Order Bandpass $\Delta\Sigma$ Time-to-Digital Converter With Negative Time-Mode Feedback.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Selecting the Fastest Settling-Time Filter in PDM-based DACs used for Dynamic Calibration Applications.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Investigating the Developments on the Frequency Compensation Techniques of the Two-Stage OTAs - A Brief Guide and Updated Review -.
Proceedings of the 31st International Conference on Microelectronics, 2019
On the Design of DACs for Dynamic Calibration Applications using Periodic Sequences from ΣΔ Modulators.
Proceedings of the 2019 IEEE Canadian Conference of Electrical and Computer Engineering, 2019
2018
Cascade and LC Ladder-Based Filter Realizations Using Synchronous Time-Mode Signal Processing.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Design of High-Order Type-II Delay-Locked Loops With a Fast-Settling-Zero-Overshoot Step Response and Large Jitter-Rejection Capabilities.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A coherent subsampling test system arrangement suitable for phase domain measurements.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
An All-Digital High-Resolution Programmable Time-Difference Amplifier Based on Time Latch.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Passive sensors for flexible hybrid-printed electronics' systems: An IC designer view.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
The analytic expression of the output spectrum of ΔΣ ADCs with nonlinear binary-weighted DACs and Gaussian input signals.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
A Top-Down Design Methodology Encompassing Components Variations Due to Wide-Range Operation in Frequency Synthesizer PLLs.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Synthesis of High Gain Operational Transconductance Amplifiers for Closed-Loop Operation Using a Generalized Controller-Based Compensation Method.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A Jitter Injection Signal Generation and Extraction System for Embedded Test of High-Speed Data I/O.
J. Electron. Test., 2016
A digitally programmable 50-150dB DC gain operational transconductance amplifier in 130nm CMOS.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Top-down design and synthesis of inherently-stable integrator-based high-order amplifiers.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Experimental operation of time-mode building blocks using a time-mode switched-delay unit.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Test Conference, 2016
Design of high-order type-II delay-locked loops using a Gaussian transfer function approach.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
An Ultra-Low-Voltage CMOS Process-Insensitive Self-Biased OTA With Rail-to-Rail Input Range.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Guest Editors' Introduction: Speeding Up Analog Integration and Test for Mixed-Signal SoCs.
IEEE Des. Test, 2015
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
A 0.55-V 1-GHz frequency synthesizer PLL for ultra-low-voltage ultra-low-power applications.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the European Conference on Circuit Theory and Design, 2015
2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
All-digital Time-Mode elliptic filters based on the operational simulation of LC ladders.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Towards a general purpose mixed-signal instrumentation layer in the die stack of a 3D-SIC.
Proceedings of the 19th IEEE European Test Symposium, 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
Sub-gate-delay edge-control of a clock signal using DLLs and ΣΔ modulation techniques.
Proceedings of the IEEE 27th Canadian Conference on Electrical and Computer Engineering, 2014
Optimization of LC-VCO tuning range under different inductor/varactor losses limitations.
Proceedings of the IEEE 27th Canadian Conference on Electrical and Computer Engineering, 2014
2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Analytical comparison between passive loop filter topologies for frequency synthesizer PLLs.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
Anti-Imaging Time-Mode Filter Design Using a PLL Structure With Transfer Function DFT.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
J. Electron. Test., 2012
A 30-40 GHz fractional-N frequency synthesizer development using a Verilog-A high-level design methodology.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
A probabilistic test instrument using a ΣΔ-encoded amplitude/phase-signal generation technique.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Programmable phase/frequency generator for system debug and diagnosis using the IEEE 1149.1 test bus.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
IEEE Des. Test Comput., 2009
Optimizing CMOS Amplifier Design Directly in SPICE without the Need for Additional Mathematical Models.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008
Proceedings of the 2008 IEEE International Test Conference, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
IEEE J. Solid State Circuits, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
Low-Voltage Analog Switch in Deep Submicron CMOS: Design Technique and Experimental Measurements.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
A Predictable Robust Fully Programmable Analog Gaussian Noise Source for Mixed-Signal/Digital ATE.
Proceedings of the 2006 IEEE International Test Conference, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
2005
Reducing Measurement Uncertainty in a DSP-Based Mixed-Signal Test Environment Without Increasing Test Time.
IEEE Trans. Very Large Scale Integr. Syst., 2005
Low power delta-sigma Modulator for ADSL applications in a low-Voltage CMOS technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
Low-voltage CMOS analog bootstrapped switch for sample-and-hold circuit: design and chip characterization.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
A High-Throughput 5 GBps Timing and Jitter Test Module Featuring Localized Processing.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A calibration technique for a high-resolution flash time-to-digital converter.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
IEEE Trans. Instrum. Meas., 2003
ITC Highlights.
IEEE Des. Test Comput., 2003
ITC 2003: Breaking Test Interface Bottlenecks.
IEEE Des. Test Comput., 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
An 8-channel, 12-bit, 20 MHz fully differential tester IC for analog and mixed-signal circuits.
Proceedings of the ESSCIRC 2003, 2003
A 5-channel, variable resolution, 10-GHz sampling rate coherent tester/oscilloscope IC and associated test vehicles.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
A 4-GHz effective sample rate integrated test core for analog and mixed-signal circuits.
IEEE J. Solid State Circuits, 2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
A deep sub-micron timing measurement circuit using a single-stage Vernier delay line.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
2001
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001
A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001
A robust DC current generation and measurement technique for deep submicron circuits.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
A 1-V, 10-bit rail-to-rail successive approximation analog-to-digital converter in standard 0.18 um CMOS technology.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
A CMOS digitally programmable current steering semidigital FIR reconstruction filter.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
2000
Increasing the performance of arbitrary waveform generators using periodic sigma-delta modulated streams.
IEEE Trans. Instrum. Meas., 2000
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Low power/low voltage high speed CMOS differential track and latch comparator with rail-to-rail input.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
1999
IEEE J. Solid State Circuits, 1999
IEEE J. Solid State Circuits, 1999
IEEE Commun. Mag., 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
1998
An integration of memory-based analog signal generation into current DFT architectures.
IEEE Trans. Instrum. Meas., 1998
On-chip measurement of the jitter transfer function of charge-pump phase-locked loops.
IEEE J. Solid State Circuits, 1998
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
Increasing the performance of arbitrary waveform generators using sigma-delta coding techniques.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
1997
IEEE J. Solid State Circuits, 1997
Int. J. Circuit Theory Appl., 1997
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997
1996
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996
1995
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
1994
A BIST technique for a frequency response and intermodulation distortion test of a sigma-delta ADC.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
1993
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993
Towards Built-In-Self-Test for SNR Testing of a Mixed-Signal IC.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
A 5th Order Bilinear Switched-current Chebyshev Filter.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
A High-Quality Analog Oscillator Using Oversampling D/A Conversion Techniques.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Designing Operational Transconductance Amplifiers for Low Voltage Operation.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Predicting Harmonic Distortion in Switched-current Memory Circuits.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993