Ondrej Cekan

According to our database, Ondrej Cekan authored at least 23 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Principy generování testovacích stimulů ; Principles of test stimuli generation.

Ondrej Cekan

PhD thesis, 2024

2021

Testing Embedded Software Through Fault Injection: Case Study on Smart Lock.

Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek

Proceedings of the 22nd IEEE Latin American Test Symposium, 2021

2020

Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks.

Jakub Podivinsky, Jakub Lojda, Richard Panek, Ondrej Cekan, Martin Krcma, Zdenek Kotásek

Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

Iterative Algorithm for Multidimensional Pareto Frontiers Intersection Determination.

Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek

Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

Analysis of Software-Implemented Fault Tolerance: Case Study on Smart Lock.

Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek

Proceedings of the IEEE East-West Design & Test Symposium, 2020

Hardening of Smart Electronic Lock Software against Random and Deliberate Faults.

Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek

Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

Automatic Design of Reliable Systems Based on the Multiple-choice Knapsack Problem.

Jakub Lojda, Jakub Podivinsky, Ondrej Cekan, Richard Panek, Martin Krcma, Zdenek Kotásek

Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020

2019

Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study.

Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards.

Ondrej Cekan, Jakub Podivinsky, Jakub Lojda, Richard Panek, Martin Krcma, Zdenek Kotásek

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

2018

A Processor Optimization Framework for a Selected Application.

Jalab Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek

Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

Input and Output Generation for the Verification of ALU: A Use Case.

Ondrej Cekan, Richard Panek, Zdenek Kotásek

Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-Based Experimental Robot Controller.

Jakub Podivinsky, Jakub Lojda, Ondrej Cekan, Zdenek Kotásek

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant System Design Automation.

Jakub Lojda, Jakub Podivinsky, Ondrej Cekan, Richard Panek, Zdenek Kotásek

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Program Generation Through a Probabilistic Constrained Grammar.

Ondrej Cekan, Jakub Podivinsky, Zdenek Kotásek

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2017

Functional verification based platform for evaluating fault tolerance properties.

Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Marcela Zachariásová, Martin Krcma, Zdenek Kotásek

Microprocess. Microsystems, 2017

Reliability Analysis and Improvement of FPGA-Based Robot Controller.

Jakub Podivinsky, Jakub Lojda, Ondrej Cekan, Richard Panek, Zdenek Kotásek

Proceedings of the Euromicro Conference on Digital System Design, 2017

A Probabilistic Context-Free Grammar Based Random Test Program Generation.

Ondrej Cekan, Zdenek Kotásek

Proceedings of the Euromicro Conference on Digital System Design, 2017

2016

Functional verification as a tool for monitoring impact of faults in SRAM-based FPGAs.

Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Zdenek Kotásek

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Random stimuli generation based on a stochastic context-free grammar.

Ondrej Cekan, Jakub Podivinsky, Zdenek Kotásek

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Verification of Robot Controller for Evaluating Impacts of Faults in Electro-Mechanical Systems.

Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Zdenek Kotásek

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015

Software Fault Tolerance: The Evaluation by Functional Verification.

Ondrej Cekan, Jakub Podivinsky, Zdenek Kotásek

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

FPGA Prototyping and Accelerated Verification of ASIPs.

Jakub Podivinsky, Marcela Simková, Ondrej Cekan, Zdenek Kotásek

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014

The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-Mechanical Applications.

Jakub Podivinsky, Ondrej Cekan, Marcela Simková, Zdenek Kotásek

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014