Zdenek Kotásek

According to our database1, Zdenek Kotásek authored at least 65 papers between 1995 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2017
Functional verification based platform for evaluating fault tolerance properties.
Microprocessors and Microsystems - Embedded Hardware Design, 2017

Comparison of FPNNs models approximation capabilities and FPGA resources utilization.
Proceedings of the 13th IEEE International Conference on Intelligent Computer Communication and Processing, 2017

Data types and operations modifications: A practical approach to fault tolerance in HLS.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

Redundant data types and operations in HLS and their use for a robot controller unit fault tolerance evaluation.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

Triple modular redundancy used in field programmable neural networks.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

Reliability Analysis and Improvement of FPGA-Based Robot Controller.
Proceedings of the Euromicro Conference on Digital System Design, 2017

A Probabilistic Context-Free Grammar Based Random Test Program Generation.
Proceedings of the Euromicro Conference on Digital System Design, 2017

2016
Functional verification as a tool for monitoring impact of faults in SRAM-based FPGAs.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

HLS-based fault tolerance approach for SRAM-based FPGAs.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Implementation of fault tolerant techniques into FPNNs.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Random stimuli generation based on a stochastic context-free grammar.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Regression Test Suites Optimization for Application-specific Instruction-Set Processors and Their Use for Dependability Analysis.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Verification of Robot Controller for Evaluating Impacts of Faults in Electro-Mechanical Systems.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015
The evaluation platform for testing fault-tolerance methodologies in electro-mechanical applications.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

Fault tolerant Field Programmable Neural Networks.
Proceedings of the Nordic Circuits and Systems Conference, 2015

Automation and Optimization of Coverage-driven Verification.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Software Fault Tolerance: The Evaluation by Functional Verification.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

FPGA Prototyping and Accelerated Verification of ASIPs.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

Mapping Trained Neural Networks to FPNNs.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

Application of Evolutionary Algorithms for Regression Suites Optimization.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014
State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-Mechanical Applications.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Automatic Construction of On-line Checking Circuits Based on Finite Automata.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Generic partial dynamic reconfiguration controller for transient and permanent fault mitigation in fault tolerant systems implemented into FPGA.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2013
Fault tolerant system design and SEU injection based testing.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

Automated Functional Verification of Application Specific Instruction-set Processors.
Proceedings of the Embedded Systems: Design, Analysis and Verification, 2013

Methodology for Fault Tolerant System Design Based on FPGA into Limited Redundant Area.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Fault tolerant CAN bus control system implemented into FPGA.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Analysis and comparison of functional verification and ATPG for testing design reliability.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012
pecial CAI Section Devoted to MEMICS '11: Preface.
Computing and Informatics, 2012

Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Test platform for fault tolerant systems design properties verification.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Advanced fault tolerant bus for multicore system implemented in FPGA.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Decreasing test time by scan chain reorganization.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010
The Use of Genetic Algorithm to Reduce Power Consumption during Test Application.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2010

Fault Tolerant Structure for SRAM-Based FPGA via Partial Dynamic Reconfiguration.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Reduction of power dissipation through parallel optimization of test vector and scan register sequences.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009
Preface.
Electr. Notes Theor. Comput. Sci., 2009

High Availability Fault Tolerant Architectures Implemented into FPGAs.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008
Evolution of synthetic RTL benchmark circuits with predefined testability.
ACM Trans. Design Autom. Electr. Syst., 2008

Testability analysis based on the identification of testable blocks with predefined properties.
Microprocessors and Microsystems - Embedded Hardware Design, 2008

Polymorphic Gates in Design and Test of Digital Circuits.
IJUC, 2008

Measuring CADeT Performance by Means of FITTest_BENCH06 Benchmark Circuits.
Computing and Informatics, 2008

Digital Systems Architectures Based on On-line Checkers.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Power Conscious RTL Test Scheduling.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007
Online Protocol Testing for FPGA Based Fault Tolerant Systems.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Checker Design for On-line Testing of Xilinx FPGA Communication Protocols.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006
SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System.
Proceedings of the 13th Annual IEEE International Conference and Workshop on Engineering of Computer Based Systems (ECBS 2006), 2006

Testability Estimation Based on Controllability and Observability Parameters.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational Modules.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage.
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006

2005
Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties.
Proceedings of the 2005 NASA / DoD Conference on Evolvable Hardware (EH 2005), 29 June, 2005

Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2004
The Identification of registers in RTL Structures for the Test Application.
Proceedings of the International Symposium on Leveraging Applications of Formal Methods, 2004

2003
Test scheduling for embedded systems.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

2002
Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

1997
RT Level Test Scheduling.
Computers and Artificial Intelligence, 1997

RT level testability analysis to reduce test application time.
Proceedings of the 23rd EUROMICRO Conference '97, 1997

1995
I-Path Analysis.
Computers and Artificial Intelligence, 1995


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