P. Sasipriya

According to our database, P. Sasipriya authored at least 4 papers between 2015 and 2026.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of six.

2026

Design and Analysis of a High-Speed Approximate Restoring Array Based Log Divider (ARLD).

P. Gowtham, A. Anita Angeline, P. Sasipriya

Circuits Syst. Signal Process., January, 2026

2018

Design and Analysis of Clocked CMOS Differential Adiabatic Logic (CCDAL) for Low Power.

P. Sasipriya, Kanchana Bhaaskaran Vettuvanam Somasundaram

J. Low Power Electron., 2018

Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL).

P. Sasipriya, V. S. Kanchana Bhaaskaran

J. Circuits Syst. Comput., 2018

2015

Two phase sinusoidal power clocked quasi-static adiabatic logic families.

P. Sasipriya, V. S. Kanchana Bhaaskaran

Proceedings of the Eighth International Conference on Contemporary Computing, 2015