V. S. Kanchana Bhaaskaran

According to our database1, V. S. Kanchana Bhaaskaran authored at least 24 papers between 2006 and 2020.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2020
Analysis of FinFET-Based Adiabatic Circuits for the Design of Arithmetic Structures.
J. Circuits Syst. Comput., 2020

Borrow Select Subtractor for Low Power and Area Efficiency.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

2019
Design of FinFET-based Energy Efficient Pass-Transistor Adiabatic Logic for ultra-low power applications.
Microelectron. J., 2019

Hardware footprints of S-box in lightweight symmetric block ciphers for IoT and CPS information security systems.
Integr., 2019

Charge balancing symmetric pre-resolve adiabatic logic against power analysis attacks.
IET Inf. Secur., 2019

Design impacts of delay invariant high-speed clock delayed dual keeper domino circuit.
IET Circuits Devices Syst., 2019

2018
Design and Analysis of Clocked CMOS Differential Adiabatic Logic (CCDAL) for Low Power.
J. Low Power Electron., 2018

Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL).
J. Circuits Syst. Comput., 2018

Lightweight S-Box Architecture for Secure Internet of Things.
Inf., 2018

Positive Feedback Symmetric Adiabatic Logic Against Differential Power Attack.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Energy Recovery Circuit Design for Low Power VLSI.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

2017
Design and Implementation of 32-Bit High Valency Jackson Adders.
J. Circuits Syst. Comput., 2017

Low-Power High-Accuracy Fixed-Width Radix-8 Booth Multiplier Using Probabilistic Estimation Technique.
J. Circuits Syst. Comput., 2017

2016
Low Power, High Speed and Area Efficient Binary Count Multiplier.
J. Circuits Syst. Comput., 2016

Self-gated resonant-clocked flip-flop optimised for power efficiency and signal integrity.
IET Circuits Devices Syst., 2016

2015
Gating techniques for 6T SRAM cell using different modes of FinFET.
Proceedings of the 2015 International Conference on Advances in Computing, 2015

Two phase sinusoidal power clocked quasi-static adiabatic logic families.
Proceedings of the Eighth International Conference on Contemporary Computing, 2015

2014
Low power vedic multiplier using energy recovery logic.
Proceedings of the 2014 International Conference on Advances in Computing, 2014

Low power divider using vedic mathematics.
Proceedings of the 2014 International Conference on Advances in Computing, 2014

Design and analysis of program counter using finite state machine and incrementer based logic.
Proceedings of the 2014 International Conference on Advances in Computing, 2014

2012
Pre-Resolve and Sense Adiabatic Logic for 100 kHz to 500 MHz Frequency Classes.
J. Circuits Syst. Comput., 2012

2010
Two-Phase sinusoidal Power-Clocked Quasi-Adiabatic Logic Circuits.
J. Circuits Syst. Comput., 2010

2008
Differential Cascode Adiabatic Logic Structure for Low Power.
J. Low Power Electron., 2008

2006
Semi-Custom Design of Adiabatic Adder Circuits.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006


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