P. V. Srinivas

According to our database1, P. V. Srinivas authored at least 4 papers between 1993 and 2006.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2006
Chip assembly: a new paradigm in hierarchical physical design.
Proceedings of the 2006 International Symposium on Physical Design, 2006

2004
Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

2003
Noise-Aware Driver Modeling for Nanometer Technology.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

1993
LATCHECK: A Latchup Checker for VLSI Layouts.
Proceedings of the Sixth International Conference on VLSI Design, 1993


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