Xiaoliang Bai

According to our database1, Xiaoliang Bai
  • authored at least 25 papers between 1999 and 2015.
  • has a "Dijkstra number"2 of four.

Timeline

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Links

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Bibliography

2015
An effective subpart retrieval approach of 3D CAD models for manufacturing process reuse.
Computers in Industry, 2015

2013
Retrieving 3D Model Using Compound-Eye Visual Representation.
Proceedings of the 2013 International Conference on Computer-Aided Design and Computer Graphics, 2013

Multi-level Structuralized MBD Model for Manufacturing Reuse of Mechanical Parts.
Proceedings of the 2013 International Conference on Computer-Aided Design and Computer Graphics, 2013

2012
A new statistical setup and hold time definition.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2011
The Spherical Images of Triangular Mesh Surfaces.
Proceedings of the 12th International Conference on Computer-Aided Design and Computer Graphics, 2011

2010
Hierarchical Parameterization of Triangular Mesh with a Boundary Polygon Triangulation.
Int. J. Image Graphics, 2010

2008
A Shape Distributions Retrieval Algorithm of 3D CAD Models Based on Normal Direction.
Proceedings of the 9th International Conference for Young Computer Scientists, 2008

2007
Evaluating Transient Error Effects in Digital Nanometer Circuits.
IEEE Trans. Reliability, 2007

A Modified SOFM Segmentation Method in Reverse Engineering.
Proceedings of the 8th ACIS International Conference on Software Engineering, 2007

3D model matching combining topology and shape features.
Proceedings of the IEEE International Conference on Robotics and Biomimetics, 2007

2005
Soft-Spot Analysis: Targeting Compound Noise Effects in Nanometer Circuits.
IEEE Design & Test of Computers, 2005

A static noise impact analysis methodology for evaluating transient error effects in digital VLSI circuits.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004
High-level crosstalk defect Simulation methodology for system-on-chip interconnects.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

An Integrated Memory Self Test and EDA Solution.
Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits.
Proceedings of the 41th Design Automation Conference, 2004

2003
HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Noise-Aware Driver Modeling for Nanometer Technology.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Software-based self-test methodology for crosstalk faults in processors.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

2002
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores.
J. Electronic Testing, 2002

Uncertainty-aware circuit optimization.
Proceedings of the 39th Design Automation Conference, 2002

2001
High-level Crosstalk Defect Simulation for System-on-Chip Interconnects.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores.
Proceedings of the 38th Design Automation Conference, 2001

2000
Self-test methodology for at-speed test of crosstalk in chip interconnects.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Fault modeling and simulation for crosstalk in system-on-chip interconnects.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999


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