Pallavi Das

According to our database, Pallavi Das authored at least 3 papers between 2014 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2016

Mixed Mode Simulation and Verification of SSCG PLL through Real Value Modeling.

Pallavi Das, Jitendra Yadav, Sujay Deb

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2015

Area compact 5T portless SRAM cell for high density cache in 65nm CMOS.

Jitendra Yadav, Pallavi Das, Abhinav Jain, Anuj Grover

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2014

Non linear sparse recovery algorithm.

Pallavi Das, Mansi Jain, Angshul Majumdar

Proceedings of the 2014 IEEE International Symposium on Signal Processing and Information Technology, 2014