Anuj Grover

According to our database1, Anuj Grover authored at least 31 papers between 2013 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
ChaCha20-in-Memory for Side-Channel Resistance in IoT Edge-Node Devices.
IEEE Open J. Circuits Syst., 2021

A 0.4µA Offset, 6ns Sensing-time Multi-level Sense Amplifier for Resistive Non-Volatile Memories in 65nm LSTP Technology.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

Reduced March iC- Test for Detecting Ageing Induced Faults in Memory Address Decoders.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

Charge Scavenging Gate Coupled Hierarchical Bitline Scheme for Ultra-Low Power SRAMs in 65nm LSTP CMOS.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

Process Compensated Diagnostic Circuit For Impending Fault Detection In SRAM Write Drivers.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

2020
Design of Sense Amplifier for Wide Voltage Range Operation of Split Supply Memories in 22nm HKMG CMOS Technology.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

Comparative Analysis and Implementation of Single-ended Sense Amplifier Schemes using 65nm LSTP CMOS Technology.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

A 0.9V 64Mb 6T SRAM cell with Read and Write assist schemes in 65nm LSTP technology.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

A 0.47V-1.17V 32KB Timing Speculative SRAM in 28nm HKMG CMOS.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

Design & Benchmark of Single Bit & Multi Bit Sequential Elements in 65nm for Low Standby Power Consumption.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

Diagnostic Circuit for Latent Fault Detection in SRAM Row Decoder.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

A 800MHz, O.21pJ, 1.2V to 6V Level Shifter Using Thin Gate Oxide Devices in 65nm LSTP.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2018
A 81nW Error Amplifier Design for Ultra Low Leakage Retention Mode Operation of 4Mb SRAM Array in 40nm LSTP Technology.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

2017
LoCCo-Based Scan Chain Stitching for Low-Power DFT.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Comparison of SRAM Cell Layout Topologies to Estimate Improvement in SER Robustness in 28FDSOI and 40 nm Technologies.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2016
A New Sense Amplifier Topology with Improved Performance for High Speed SRAM Applications.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

New stable loadless 6T dual-port SRAM cell design.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

An effective test methodology enabling detection of weak bits in SRAMs: Case study in 28nm FDSOI.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

Heterogeneous memory assembly exploration using a floorplan and interconnect aware framework.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

A method to estimate effectiveness of weak bit test: Comparison of weak pMOS and WL boost based test - 28nm FDSOI implementation.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Static Noise Margin based Yield Modelling of 6T SRAM for Area and Minimum Operating Voltage Improvement using Recovery Techniques.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Scan Chain Adaptation through ECO.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking.
IEEE J. Solid State Circuits, 2015

Statistical Analysis of 64Mb SRAM for Optimizing Yield and Write Performance.
Proceedings of the 28th International Conference on VLSI Design, 2015

Area compact 5T portless SRAM cell for high density cache in 65nm CMOS.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Floorplan and congestion aware framework for optimal SRAM selection for memory subsystems.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

2014

2013
Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology.
Proceedings of 2013 International Conference on IC Design & Technology, 2013



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