Anuj Grover
Orcid: 0000-0002-6057-4984
According to our database1,
Anuj Grover
authored at least 37 papers
between 2013 and 2023.
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Bibliography
2023
A Common Mode Insensitive Process Tolerant Sense Amplifier Design for In Memory Compute Applications in 65nm LSTP Technology.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
A Sense Amplifier Based Bulk Built-In Current Sensor for Detecting Laser-Induced Currents.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
2022
Retention Problem Free High Density 4T SRAM cell with Adaptive Body Bias in 18nm FD-SOI.
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Up to 13.7% Increase in Throughput of RISC V SoC Using Timing Speculative Razor SRAM.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
A Process and Data Variations Tolerant Capacitive Coupled 10T1C SRAM for In-Memory Compute (IMC) in Deep Neural Network Accelerators.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
IEEE Open J. Circuits Syst., 2021
A 0.4µA Offset, 6ns Sensing-time Multi-level Sense Amplifier for Resistive Non-Volatile Memories in 65nm LSTP Technology.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021
Reduced March iC- Test for Detecting Ageing Induced Faults in Memory Address Decoders.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021
Charge Scavenging Gate Coupled Hierarchical Bitline Scheme for Ultra-Low Power SRAMs in 65nm LSTP CMOS.
Proceedings of the 28th IEEE International Conference on Electronics, 2021
Process Compensated Diagnostic Circuit For Impending Fault Detection In SRAM Write Drivers.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021
2020
Design of Sense Amplifier for Wide Voltage Range Operation of Split Supply Memories in 22nm HKMG CMOS Technology.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
Comparative Analysis and Implementation of Single-ended Sense Amplifier Schemes using 65nm LSTP CMOS Technology.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020
Design & Benchmark of Single Bit & Multi Bit Sequential Elements in 65nm for Low Standby Power Consumption.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
A 800MHz, O.21pJ, 1.2V to 6V Level Shifter Using Thin Gate Oxide Devices in 65nm LSTP.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
2018
A 81nW Error Amplifier Design for Ultra Low Leakage Retention Mode Operation of 4Mb SRAM Array in 40nm LSTP Technology.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Comparison of SRAM Cell Layout Topologies to Estimate Improvement in SER Robustness in 28FDSOI and 40 nm Technologies.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
2016
A New Sense Amplifier Topology with Improved Performance for High Speed SRAM Applications.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
An effective test methodology enabling detection of weak bits in SRAMs: Case study in 28nm FDSOI.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
Heterogeneous memory assembly exploration using a floorplan and interconnect aware framework.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
A method to estimate effectiveness of weak bit test: Comparison of weak pMOS and WL boost based test - 28nm FDSOI implementation.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
Static Noise Margin based Yield Modelling of 6T SRAM for Area and Minimum Operating Voltage Improvement using Recovery Techniques.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 25th IEEE Asian Test Symposium, 2016
2015
IEEE J. Solid State Circuits, 2015
Proceedings of the 28th International Conference on VLSI Design, 2015
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
Floorplan and congestion aware framework for optimal SRAM selection for memory subsystems.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology.
Proceedings of 2013 International Conference on IC Design & Technology, 2013
Proceedings of the Design, Automation and Test in Europe, 2013