Paras Garg

According to our database, Paras Garg authored at least 3 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

Three-Level Output Side Gate Driver for 1 V Thin-Gate-Oxide NMOSFET Switch in a SIDO Converter.

Abhijit Keshri, Pramit Banerjee, Gautam Dey Kanungo, Kallol Chatterjee, Paras Garg, Santanu Kapat, Debashis Mandal

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024

A Novel 2.7 pJ/bit, Low Supply, Power Efficient, Wide-Range 2.5-6 Gb/s Transmitter for 4-Channel High-Speed Serial Transmit Port (HSSTP) in 28nm FD-SOI Technology.

Sameer Vashishtha, Prashant Kumar Singh, Mohd. Rizvi, Paras Garg

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Loop Filter Design Considerations for Noise-Shaping in SAR ADCs.

Anamika Sharma, Luv Pandey, Paras Garg, Rajesh Zele

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024