Paras Garg

According to our database, Paras Garg authored at least 5 papers between 2024 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

A Partially Loop-Unrolled Noise-Shaping SAR ADC Achieving 57dB-SNDR in 40MHz-BW at 320MS/s in 18nm FD-SOI CMOS Technology.

Anamika Sharma, Luv Pandey, Paras Garg, Rajesh Zele

Proceedings of the 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems, 2026

A 1.16GHz -160.4dBFS/Hz-NSD multi-bit Continuous-Time Delta-Sigma ADC Achieving SNR/SNDR of 86dB/83dB in 17.5MHz-BW without DAC calibration.

Vaibhav Garg, Paras Garg, Ankur Bal, Sanyam Jain, Frédéric Paillardet, Kallol Chatterjee, Chandrajit Debnath, Gauri Mittal, Anand Kumar

Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

2025

Three-Level Output Side Gate Driver for 1 V Thin-Gate-Oxide NMOSFET Switch in a SIDO Converter.

Abhijit Keshri, Pramit Banerjee, Gautam Dey Kanungo, Kallol Chatterjee, Paras Garg, Santanu Kapat, Debashis Mandal

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024

A Novel 2.7 pJ/bit, Low Supply, Power Efficient, Wide-Range 2.5-6 Gb/s Transmitter for 4-Channel High-Speed Serial Transmit Port (HSSTP) in 28nm FD-SOI Technology.

Sameer Vashishtha, Prashant Kumar Singh, Mohd. Rizvi, Paras Garg

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Loop Filter Design Considerations for Noise-Shaping in SAR ADCs.

Anamika Sharma, Luv Pandey, Paras Garg, Rajesh Zele

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024