Debashis Mandal

According to our database1, Debashis Mandal authored at least 22 papers between 2005 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2021
Towards an Ontology for Enterprise Level Information Security Policy Analysis.
Proceedings of the 7th International Conference on Information Systems Security and Privacy, 2021

2019
Low-Power/Low-Voltage Integrated CMOS Sense Resistor-Free Analog Power/Current Sensor Compatible With High-Voltage Switching DC-DC Converter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Adaptively Biased Output Cap-Less NMOS LDO With 19 ns Settling Time.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 50-V Isolation, 100-MHz, 50-mW Single-Chip Junction Isolated DC-DC Converter With Self-Tuned Maximum Power Transfer Frequency.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Wideband Hybrid Envelope Tracking Modulator With Hysteretic-Controlled Three-Level Switching Converter and Slew-Rate Enhanced Linear Amplifier.
IEEE J. Solid State Circuits, 2019

A 91%-Efficiency Envelope-Tracking Modulator Using Hysteresis-Controlled Three-Level Switching Regulator and Slew-Rate-Enhanced Linear Amplifier for LTE-80MHz Applications.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A Disturbance-Free Built-In Self-Test and Diagnosis Technique for DC-DC Converters.
ACM Trans. Design Autom. Electr. Syst., 2018

Online Built-In Self-Test of High Switching Frequency DC-DC Converters Using Model Reference Based System Identification Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Sense resistor-free analog power sensor for boost converter with 14.1% gain error and 9.4% offset error.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

2017
A 50-mA 99.2% Peak Current Efficiency, 250-ns Settling Time Digital Low-Dropout Regulator With Transient Enhanced PI Controller.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A 100-mA, 99.11% Current Efficiency, 2-mV<sub>pp</sub> Ripple Digitally Controlled LDO With Active Ripple Suppression.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A 6 A, 93% Peak Efficiency, 4-Phase Digitally Synchronized Hysteretic Buck Converter With ±1.5% Frequency and ±3.6% Current-Sharing Error.
IEEE J. Solid State Circuits, 2017

2015
Spur reduction in frequency synthesizer with an array of switched capacitors.
Int. J. Circuit Theory Appl., 2015

Prediction of reference spur in frequency synthesisers.
IET Circuits Devices Syst., 2015

Disturbance-free BIST for loop characterization of DC-DC buck converters.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Fully-integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

2014
Spur reducing architecture of frequency synthesiser using switched capacitors.
IET Circuits Devices Syst., 2014

2012
Spur suppression in frequency synthesizer using switched capacitor array.
Proceedings of the International SoC Design Conference, 2012

2008
Implementation of CMOS Low-power Integer-N Frequency Synthesizer for SOC Design.
J. Comput., 2008

2007
7.95mW 2.4GHz Fully-Integrated CMOS Integer N Frequency Synthesizer.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006
Development of a Wireless Integrated Toxic and Explosive MEMS Based Gas Sensor.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2005
High voltage tolerant output buffer design for mixed voltage interfaces.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


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