Paresh Baidya

According to our database, Paresh Baidya authored at least 7 papers between 2022 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

Error Detection Schemes for Barrett Reduction of CT-BU on FPGA in Post Quantum Cryptography.

Paresh Baidya, Rourab Paul, Vikas Srivastava, Sumit Kumar Debnath

CoRR, September, 2025

Lightweight Fault Detection Architecture for NTT on FPGA.

Rourab Paul, Paresh Baidya, Krishnendu Guha

CoRR, August, 2025

Energy-Efficient NTT Sampler for Kyber Benchmarked on FPGA.

Paresh Baidya, Rourab Paul, Vikas Srivastava, Sumit Kumar Debnath

CoRR, May, 2025

2024

Efficient Implementation of Knuth Yao Sampler on Reconfigurable Hardware.

Paresh Baidya, Rourab Paul, Swagata Mandal, Sumit Kumar Debnath

IEEE Comput. Archit. Lett., 2024

Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Hardware Accelerator on Reconfigurable Architecture.

Paresh Baidya, Swagata Mandal, Rourab Paul

IEEE Access, 2024

2023

Blockchain-Envisioned Post-Quantum Secure Sanitizable Signature for Audit Logs Management.

Vikas Srivastava, Paresh Baidya, Sumit Kumar Debnath, Sihem Mesnager

CoRR, 2023

2022

Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Post Quantum Cryptography on Reconfigurable Architecture.

Paresh Baidya, Swagata Mandal, Rourab Paul

CoRR, 2022