Rourab Paul

Orcid: 0000-0001-5322-281X

According to our database1, Rourab Paul authored at least 33 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
Power Aware Scheduling of Tasks on FPGAs in Data Centers.
Proceedings of the 32nd Euromicro International Conference on Parallel, 2024

2023
Smart contract assisted blockchain based public key infrastructure system.
Trans. Emerg. Telecommun. Technol., January, 2023

2022
HealthCare EHR: A Blockchain-Based Decentralized Application.
Int. J. Inf. Syst. Supply Chain Manag., 2022

Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Post Quantum Cryptography on Reconfigurable Architecture.
CoRR, 2022

Smart Contract Assisted Blockchain based PKI System.
CoRR, 2022

CTB-PKI: Clustering and Trust Enabled Blockchain Based PKI System for Efficient Communication in P2P Network.
IEEE Access, 2022

2021
<i>iDCR</i>: Improved Dempster Combination Rule for multisensor fault diagnosis.
Eng. Appl. Artif. Intell., 2021

Voltage Scaling for Partitioned Systolic Array in A Reconfigurable Platform.
CoRR, 2021

Blockchain based secure smart city architecture using low resource IoTs.
Comput. Networks, 2021

2020
<i>Fault Matters</i>: Sensor data fusion for detection of faults using Dempster-Shafer theory of evidence in IoT-based applications.
Expert Syst. Appl., 2020

The Blockchain Based Auditor on Secret key Life Cycle in Reconfigurable Platform.
CoRR, 2020

iDCR: Improved Dempster Combination Rule for Multisensor Fault Diagnosis.
CoRR, 2020

2019
IoT based Smart Access Controlled Secure Smart City Architecture Using Blockchain.
CoRR, 2019

Fault Matters: Sensor Data Fusion for Detection of Faults using Dempster-Shafer Theory of Evidence in IoT-Based Applications.
CoRR, 2019

2018
Hardware variant NSP with security-aware automated preferential algorithm.
IET Comput. Digit. Tech., 2018

Partitioned security processor architecture on FPGA platform.
IET Comput. Digit. Tech., 2018

2017
Efficient dynamic priority based soft error mitigation techniques for configuration memory of FPGA hardware.
Microprocess. Microsystems, 2017

A High Speed KECCAK Coprocessor for Partitioned NSP Architecture on FPGA Platform.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2016
Multi core SSL/TLS security processor architecture and its FPGA prototype design with automated preferential algorithm.
Microprocess. Microsystems, 2016

A Novel Method for Soft Error Mitigation in FPGA Using Modified Matrix Code.
IEEE Embed. Syst. Lett., 2016

Accelerating More Secure RC4 : Implementation of Seven FPGA Designs in Stages upto 8 byte per clock.
CoRR, 2016

Error Resilient Secure Multi-gigabit Optical Link Design for High Energy Physics Experiment.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2015
A Novel Method for Soft Error Mitigation in FPGA using Adaptive Cross Parity Code.
CoRR, 2015

Multicore encryption and authentication on a reconfigurable hardware.
Proceedings of the 2nd IEEE International Conference on Recent Trends in Information Systems, 2015

2014
Multi Core SSL/TLS Security Processor Architecture Prototype Design with automated Preferential Algorithm in FPGA.
CoRR, 2014

Fault Detection for RC4 Algorithm and its Implementation on FPGA Platform.
CoRR, 2014

Hardware Implementation of four byte per clock RC4 algorithm.
CoRR, 2014

Performance Evaluation of ECC in Single and Multi Processor Architectures on FPGA Based Embedded System.
CoRR, 2014

2012
A brief experience on journey through hardware developments for image processing and its applications on Cryptography
CoRR, 2012

Architecture for real time continuous sorting on large width data volume for fpga based applications
CoRR, 2012

Design and implementation of real time AES-128 on real time operating system for multiple FPGA communication
CoRR, 2012

A simple 1-byte 1-clock RC4 design and its efficient implementation in FPGA coprocessor for secured ethernet communication
CoRR, 2012

A novel AES-256 implementation on FPGA using co-processor based architecture.
Proceedings of the 2012 International Conference on Advances in Computing, 2012


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