Krishnendu Guha

Orcid: 0000-0003-1139-9582

According to our database1, Krishnendu Guha authored at least 27 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
AgEncID: Aggregate Encryption Individual Decryption of Key for FPGA Bitstream IP Cores in Cloud.
CoRR, 2023

Energy Efficient Memory-based Inference of LSTM by Exploiting FPGA Overlay.
Proceedings of the International Joint Conference on Neural Networks, 2023

Blockchain Facilitated Protection and Safety in Cyberphysical Systems from Defective Sensors.
Proceedings of the 14th International Conference on Computing Communication and Networking Technologies, 2023

A Self Aware Security Approach for Real Time Neural Network Applications from Row Hammer Attacks in Multi FPGA Multi User Environment.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

2022
Criticality based Reliability from Rowhammer Attacks in Multi-User-Multi-FPGA Platform.
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

SENAS: Security driven ENergy Aware Scheduler for Real Time Approximate Computing Tasks on Multi-Processor Systems.
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

2021
Criticality based Reduction of Security Costs in a FPGA based Cloud Computing Farm.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

Self Aware Security for Real Time Task Schedules in Reconfigurable Hardware Platforms
Springer, ISBN: 978-3-030-79700-3, 2021

2020
Dynamic power-aware scheduling of real-time tasks for FPGA-based cyber physical systems against power draining hardware trojan attacks.
J. Supercomput., 2020

A Multi-Agent Co-operative Model to Facilitate Criticality based Reliability for Mixed Critical Task Execution on FPGA based Cloud Environment.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

Ensuring Green Computing in Reconfigurable Hardware based Cloud Platforms from Hardware Trojan Attacks.
Proceedings of the 2020 IEEE Region 10 Conference, 2020

Blockchain Technology Enabled Pay Per Use Licensing Approach for Hardware IPs.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Stigmergy-Based Security for SoC Operations From Runtime Performance Degradation of SoC Components.
ACM Trans. Embed. Comput. Syst., 2019

Criticality based reliability against hardware Trojan attacks for processing of tasks on reconfigurable hardware.
Microprocess. Microsystems, 2019

Zero Knowledge Authentication for Reuse of IPs in Reconfigurable Platforms.
Proceedings of the TENCON 2019, 2019

Auction Based Power Aware Real-Time Scheduler for Heterogeneous FPGA Cloud Platform.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

2018
SHIRT (Self Healing Intelligent Real Time) Scheduling for Secure Embedded Task Processing.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

SARP: Self Aware Runtime Protection Against Integrity Attacks of Hardware Trojans.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

Reliability Driven Mixed Critical Tasks Processing on FPGAs Against Hardware Trojan Attacks.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2017
Real-Time SoC Security against Passive Threats Using Crypsis Behavior of Geckos.
ACM J. Emerg. Technol. Comput. Syst., 2017

Self Aware SoC Security to Counteract Delay Inducing Hardware Trojans at Runtime.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

2016
Pre-layout module wise decap allocation for noise suppression and accurate delay estimation of SoC.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

2015
Pre-Layout Decoupling Capacitance Estimation and Allocation for Noise-Aware Crypto-System on Chip Applications.
J. Low Power Electron., 2015

RTNA: Securing SOC architectures from confidentiality attacks at runtime using ART1 neural networks.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

CAD-Based Analysis of Power Distribution Network for SOC Design.
Proceedings of the Advanced Computing and Systems for Security - ACSS 2015, 2015

2014
Analysis of power distribution network for some cryptocores.
Proceedings of the 2014 International Conference on Advances in Computing, 2014

Analysis of Secret Key Revealing Trojan Using Path Delay Analysis for Some Cryptocores.
Proceedings of the 3rd International Conference on Frontiers of Intelligent Computing: Theory and Applications (FICTA) 2014, 2014


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